]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
ARM: dts: mvebu: pl310-cache disable double-linefill
authorYan Markman <ymarkman@marvell.com>
Sat, 15 Oct 2016 21:22:32 +0000 (00:22 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 8 Nov 2017 09:17:17 +0000 (10:17 +0100)
commit cda80a82ac3e89309706c027ada6ab232be1d640 upstream.

Under heavy system stress mvebu SoC using Cortex A9 sporadically
encountered instability issues.

The "double linefill" feature of L2 cache was identified as causing
dependency between read and write which lead to the deadlock.

Especially, it was the cause of deadlock seen under heavy PCIe traffic,
as this dependency violates PCIE overtaking rule.

Fixes: c8f5a878e554 ("ARM: mvebu: use DT properties to fine-tune the L2 configuration")
Signed-off-by: Yan Markman <ymarkman@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
[gregory.clement@free-electrons.com: reformulate commit log, add Armada
375 and add Fixes tag]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm/boot/dts/armada-375.dtsi
arch/arm/boot/dts/armada-38x.dtsi
arch/arm/boot/dts/armada-39x.dtsi

index 50c5e8417802cd42c3beee13bcf9a23b3a127791..10b99530280a712b01bc22f241d9fcb71baca2c3 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
-                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-incr = <0>;
                                arm,double-linefill-wrap = <0>;
-                               arm,double-linefill = <1>;
+                               arm,double-linefill = <0>;
                                prefetch-data = <1>;
                        };
 
index af31f5d6c0e571f607fa47eb7aa00094d3ffdcb9..c3448622e79e0bf8bcbabca859126fd3d624dd8b 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
-                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-incr = <0>;
                                arm,double-linefill-wrap = <0>;
-                               arm,double-linefill = <1>;
+                               arm,double-linefill = <0>;
                                prefetch-data = <1>;
                        };
 
index 60fbfd5907c71049e75935cba303f795be38ad72..55d02641d930674f094d1f5ec1a9ec261969f5dd 100644 (file)
                                reg = <0x8000 0x1000>;
                                cache-unified;
                                cache-level = <2>;
-                               arm,double-linefill-incr = <1>;
+                               arm,double-linefill-incr = <0>;
                                arm,double-linefill-wrap = <0>;
-                               arm,double-linefill = <1>;
+                               arm,double-linefill = <0>;
                                prefetch-data = <1>;
                        };