--- /dev/null
+From c3e9826a22027a21d998d3e64882fa377b613006 Mon Sep 17 00:00:00 2001
+From: Wentao Liang <vulab@iscas.ac.cn>
+Date: Mon, 26 May 2025 10:37:31 +0800
+Subject: drm/amd/display: Add null pointer check for get_first_active_display()
+
+From: Wentao Liang <vulab@iscas.ac.cn>
+
+commit c3e9826a22027a21d998d3e64882fa377b613006 upstream.
+
+The function mod_hdcp_hdcp1_enable_encryption() calls the function
+get_first_active_display(), but does not check its return value.
+The return value is a null pointer if the display list is empty.
+This will lead to a null pointer dereference in
+mod_hdcp_hdcp2_enable_encryption().
+
+Add a null pointer check for get_first_active_display() and return
+MOD_HDCP_STATUS_DISPLAY_NOT_FOUND if the function return null.
+
+Fixes: 2deade5ede56 ("drm/amd/display: Remove hdcp display state with mst fix")
+Signed-off-by: Wentao Liang <vulab@iscas.ac.cn>
+Reviewed-by: Alex Hung <alex.hung@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org # v5.8
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
++++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+@@ -368,6 +368,9 @@ enum mod_hdcp_status mod_hdcp_hdcp1_enab
+ struct mod_hdcp_display *display = get_first_active_display(hdcp);
+ enum mod_hdcp_status status = MOD_HDCP_STATUS_SUCCESS;
+
++ if (!display)
++ return MOD_HDCP_STATUS_DISPLAY_NOT_FOUND;
++
+ mutex_lock(&psp->hdcp_context.mutex);
+ hdcp_cmd = (struct ta_hdcp_shared_memory *)psp->hdcp_context.context.mem_context.shared_buf;
+ memset(hdcp_cmd, 0, sizeof(struct ta_hdcp_shared_memory));
--- /dev/null
+From 0bbf5fd86c585d437b75003f11365b324360a5d6 Mon Sep 17 00:00:00 2001
+From: Frank Min <Frank.Min@amd.com>
+Date: Wed, 4 Jun 2025 21:00:44 +0800
+Subject: drm/amdgpu: Add kicker device detection
+
+From: Frank Min <Frank.Min@amd.com>
+
+commit 0bbf5fd86c585d437b75003f11365b324360a5d6 upstream.
+
+1. add kicker device list
+2. add kicker device checking helper function
+
+Signed-off-by: Frank Min <Frank.Min@amd.com>
+Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit 09aa2b408f4ab689c3541d22b0968de0392ee406)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 17 +++++++++++++++++
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 6 ++++++
+ 2 files changed, 23 insertions(+)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+@@ -28,6 +28,10 @@
+ #include "amdgpu.h"
+ #include "amdgpu_ucode.h"
+
++static const struct kicker_device kicker_device_list[] = {
++ {0x744B, 0x00},
++};
++
+ static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
+ {
+ DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
+@@ -1268,6 +1272,19 @@ static const char *amdgpu_ucode_legacy_n
+ return NULL;
+ }
+
++bool amdgpu_is_kicker_fw(struct amdgpu_device *adev)
++{
++ int i;
++
++ for (i = 0; i < ARRAY_SIZE(kicker_device_list); i++) {
++ if (adev->pdev->device == kicker_device_list[i].device &&
++ adev->pdev->revision == kicker_device_list[i].revision)
++ return true;
++ }
++
++ return false;
++}
++
+ void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)
+ {
+ int maj, min, rev;
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+@@ -536,6 +536,11 @@ struct amdgpu_firmware {
+ uint64_t fw_buf_mc;
+ };
+
++struct kicker_device{
++ unsigned short device;
++ u8 revision;
++};
++
+ void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
+ void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
+ void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr);
+@@ -562,5 +567,6 @@ amdgpu_ucode_get_load_type(struct amdgpu
+ const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);
+
+ void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len);
++bool amdgpu_is_kicker_fw(struct amdgpu_device *adev);
+
+ #endif
--- /dev/null
+From 4d2f6b4e4c7ed32e7fa39fcea37344a9eab99094 Mon Sep 17 00:00:00 2001
+From: John Olender <john.olender@gmail.com>
+Date: Tue, 29 Apr 2025 07:24:28 -0400
+Subject: drm/amdgpu: amdgpu_vram_mgr_new(): Clamp lpfn to total vram
+
+From: John Olender <john.olender@gmail.com>
+
+commit 4d2f6b4e4c7ed32e7fa39fcea37344a9eab99094 upstream.
+
+The drm_mm allocator tolerated being passed end > mm->size, but the
+drm_buddy allocator does not.
+
+Restore the pre-buddy-allocator behavior of allowing such placements.
+
+Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3448
+Signed-off-by: John Olender <john.olender@gmail.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Reviewed-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
+@@ -435,7 +435,7 @@ static int amdgpu_vram_mgr_new(struct tt
+ int r;
+
+ lpfn = (u64)place->lpfn << PAGE_SHIFT;
+- if (!lpfn)
++ if (!lpfn || lpfn > man->size)
+ lpfn = man->size;
+
+ fpfn = (u64)place->fpfn << PAGE_SHIFT;
--- /dev/null
+From ebe43542702c3d15d1a1d95e8e13b1b54076f05a Mon Sep 17 00:00:00 2001
+From: Alex Deucher <alexander.deucher@amd.com>
+Date: Mon, 2 Jun 2025 11:31:52 -0400
+Subject: drm/amdgpu: switch job hw_fence to amdgpu_fence
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Alex Deucher <alexander.deucher@amd.com>
+
+commit ebe43542702c3d15d1a1d95e8e13b1b54076f05a upstream.
+
+Use the amdgpu fence container so we can store additional
+data in the fence. This also fixes the start_time handling
+for MCBP since we were casting the fence to an amdgpu_fence
+and it wasn't.
+
+Fixes: 3f4c175d62d8 ("drm/amdgpu: MCBP based on DRM scheduler (v9)")
+Reviewed-by: Christian König <christian.koenig@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+(cherry picked from commit bf1cd14f9e2e1fdf981eed273ddd595863f5288c)
+Cc: stable@vger.kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 30 ++++++----------------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 12 +++++------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 2 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 16 ++++++++++++++
+ 6 files changed, 32 insertions(+), 32 deletions(-)
+
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+@@ -1890,7 +1890,7 @@ no_preempt:
+ continue;
+ }
+ job = to_amdgpu_job(s_job);
+- if (preempted && (&job->hw_fence) == fence)
++ if (preempted && (&job->hw_fence.base) == fence)
+ /* mark the job as preempted */
+ job->preemption_status |= AMDGPU_IB_PREEMPTED;
+ }
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+@@ -5367,7 +5367,7 @@ int amdgpu_device_gpu_recover(struct amd
+ *
+ * job->base holds a reference to parent fence
+ */
+- if (job && dma_fence_is_signaled(&job->hw_fence)) {
++ if (job && dma_fence_is_signaled(&job->hw_fence.base)) {
+ job_signaled = true;
+ dev_info(adev->dev, "Guilty job already signaled, skipping HW reset");
+ goto skip_hw_reset;
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+@@ -41,22 +41,6 @@
+ #include "amdgpu_trace.h"
+ #include "amdgpu_reset.h"
+
+-/*
+- * Fences mark an event in the GPUs pipeline and are used
+- * for GPU/CPU synchronization. When the fence is written,
+- * it is expected that all buffers associated with that fence
+- * are no longer in use by the associated ring on the GPU and
+- * that the relevant GPU caches have been flushed.
+- */
+-
+-struct amdgpu_fence {
+- struct dma_fence base;
+-
+- /* RB, DMA, etc. */
+- struct amdgpu_ring *ring;
+- ktime_t start_timestamp;
+-};
+-
+ static struct kmem_cache *amdgpu_fence_slab;
+
+ int amdgpu_fence_slab_init(void)
+@@ -153,12 +137,12 @@ int amdgpu_fence_emit(struct amdgpu_ring
+ am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC);
+ if (am_fence == NULL)
+ return -ENOMEM;
+- fence = &am_fence->base;
+- am_fence->ring = ring;
+ } else {
+ /* take use of job-embedded fence */
+- fence = &job->hw_fence;
++ am_fence = &job->hw_fence;
+ }
++ fence = &am_fence->base;
++ am_fence->ring = ring;
+
+ seq = ++ring->fence_drv.sync_seq;
+ if (job && job->job_run_counter) {
+@@ -719,7 +703,7 @@ void amdgpu_fence_driver_clear_job_fence
+ * it right here or we won't be able to track them in fence_drv
+ * and they will remain unsignaled during sa_bo free.
+ */
+- job = container_of(old, struct amdgpu_job, hw_fence);
++ job = container_of(old, struct amdgpu_job, hw_fence.base);
+ if (!job->base.s_fence && !dma_fence_is_signaled(old))
+ dma_fence_signal(old);
+ RCU_INIT_POINTER(*ptr, NULL);
+@@ -781,7 +765,7 @@ static const char *amdgpu_fence_get_time
+
+ static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f)
+ {
+- struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
++ struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence.base);
+
+ return (const char *)to_amdgpu_ring(job->base.sched)->name;
+ }
+@@ -811,7 +795,7 @@ static bool amdgpu_fence_enable_signalin
+ */
+ static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
+ {
+- struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
++ struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence.base);
+
+ if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer))
+ amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched));
+@@ -846,7 +830,7 @@ static void amdgpu_job_fence_free(struct
+ struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
+
+ /* free job if fence has a parent job */
+- kfree(container_of(f, struct amdgpu_job, hw_fence));
++ kfree(container_of(f, struct amdgpu_job, hw_fence.base));
+ }
+
+ /**
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+@@ -165,8 +165,8 @@ void amdgpu_job_free_resources(struct am
+ /* Check if any fences where initialized */
+ if (job->base.s_fence && job->base.s_fence->finished.ops)
+ f = &job->base.s_fence->finished;
+- else if (job->hw_fence.ops)
+- f = &job->hw_fence;
++ else if (job->hw_fence.base.ops)
++ f = &job->hw_fence.base;
+ else
+ f = NULL;
+
+@@ -183,10 +183,10 @@ static void amdgpu_job_free_cb(struct dr
+ amdgpu_sync_free(&job->explicit_sync);
+
+ /* only put the hw fence if has embedded fence */
+- if (!job->hw_fence.ops)
++ if (!job->hw_fence.base.ops)
+ kfree(job);
+ else
+- dma_fence_put(&job->hw_fence);
++ dma_fence_put(&job->hw_fence.base);
+ }
+
+ void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
+@@ -215,10 +215,10 @@ void amdgpu_job_free(struct amdgpu_job *
+ if (job->gang_submit != &job->base.s_fence->scheduled)
+ dma_fence_put(job->gang_submit);
+
+- if (!job->hw_fence.ops)
++ if (!job->hw_fence.base.ops)
+ kfree(job);
+ else
+- dma_fence_put(&job->hw_fence);
++ dma_fence_put(&job->hw_fence.base);
+ }
+
+ struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job)
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+@@ -48,7 +48,7 @@ struct amdgpu_job {
+ struct drm_sched_job base;
+ struct amdgpu_vm *vm;
+ struct amdgpu_sync explicit_sync;
+- struct dma_fence hw_fence;
++ struct amdgpu_fence hw_fence;
+ struct dma_fence *gang_submit;
+ uint32_t preamble_status;
+ uint32_t preemption_status;
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+@@ -123,6 +123,22 @@ struct amdgpu_fence_driver {
+ struct dma_fence **fences;
+ };
+
++/*
++ * Fences mark an event in the GPUs pipeline and are used
++ * for GPU/CPU synchronization. When the fence is written,
++ * it is expected that all buffers associated with that fence
++ * are no longer in use by the associated ring on the GPU and
++ * that the relevant GPU caches have been flushed.
++ */
++
++struct amdgpu_fence {
++ struct dma_fence base;
++
++ /* RB, DMA, etc. */
++ struct amdgpu_ring *ring;
++ ktime_t start_timestamp;
++};
++
+ extern const struct drm_sched_backend_ops amdgpu_sched_ops;
+
+ void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
--- /dev/null
+From c6a7ef0d4856b9629df390e9935d7fd67fe39f81 Mon Sep 17 00:00:00 2001
+From: Aradhya Bhatia <a-bhatia1@ti.com>
+Date: Sat, 29 Mar 2025 17:09:15 +0530
+Subject: drm/bridge: cdns-dsi: Check return value when getting default PHY config
+
+From: Aradhya Bhatia <a-bhatia1@ti.com>
+
+commit c6a7ef0d4856b9629df390e9935d7fd67fe39f81 upstream.
+
+Check for the return value of the phy_mipi_dphy_get_default_config()
+call, and in case of an error, return back the same.
+
+Fixes: fced5a364dee ("drm/bridge: cdns: Convert to phy framework")
+Cc: stable@vger.kernel.org
+Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Tested-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
+Signed-off-by: Aradhya Bhatia <aradhya.bhatia@linux.dev>
+Link: https://lore.kernel.org/r/20250329113925.68204-5-aradhya.bhatia@linux.dev
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
++++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+@@ -575,9 +575,11 @@ static int cdns_dsi_check_conf(struct cd
+ if (ret)
+ return ret;
+
+- phy_mipi_dphy_get_default_config(mode_clock * 1000,
+- mipi_dsi_pixel_format_to_bpp(output->dev->format),
+- nlanes, phy_cfg);
++ ret = phy_mipi_dphy_get_default_config(mode_clock * 1000,
++ mipi_dsi_pixel_format_to_bpp(output->dev->format),
++ nlanes, phy_cfg);
++ if (ret)
++ return ret;
+
+ ret = cdns_dsi_adjust_phy_config(dsi, dsi_cfg, phy_cfg, mode, mode_valid_check);
+ if (ret)
--- /dev/null
+From 688eb4d465484bc2a3471a6a6f06f833b58c7867 Mon Sep 17 00:00:00 2001
+From: Aradhya Bhatia <a-bhatia1@ti.com>
+Date: Sat, 29 Mar 2025 17:09:12 +0530
+Subject: drm/bridge: cdns-dsi: Fix connecting to next bridge
+
+From: Aradhya Bhatia <a-bhatia1@ti.com>
+
+commit 688eb4d465484bc2a3471a6a6f06f833b58c7867 upstream.
+
+Fix the OF node pointer passed to the of_drm_find_bridge() call to find
+the next bridge in the display chain.
+
+The code to find the next panel (and create its panel-bridge) works
+fine, but to find the next (non-panel) bridge does not.
+
+To find the next bridge in the pipeline, we need to pass "np" - the OF
+node pointer of the next entity in the devicetree chain. Passing
+"of_node" to of_drm_find_bridge (which is what the code does currently)
+will fetch the bridge for the cdns-dsi which is not what's required.
+
+Fix that.
+
+Fixes: e19233955d9e ("drm/bridge: Add Cadence DSI driver")
+Cc: stable@vger.kernel.org
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Tested-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
+Signed-off-by: Aradhya Bhatia <aradhya.bhatia@linux.dev>
+Link: https://lore.kernel.org/r/20250329113925.68204-2-aradhya.bhatia@linux.dev
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
++++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+@@ -958,7 +958,7 @@ static int cdns_dsi_attach(struct mipi_d
+ bridge = drm_panel_bridge_add_typed(panel,
+ DRM_MODE_CONNECTOR_DSI);
+ } else {
+- bridge = of_drm_find_bridge(dev->dev.of_node);
++ bridge = of_drm_find_bridge(np);
+ if (!bridge)
+ bridge = ERR_PTR(-EINVAL);
+ }
--- /dev/null
+From fd2611c13f69cbbc6b81d9fc7502abf4f7031d21 Mon Sep 17 00:00:00 2001
+From: Aradhya Bhatia <a-bhatia1@ti.com>
+Date: Sat, 29 Mar 2025 17:09:13 +0530
+Subject: drm/bridge: cdns-dsi: Fix phy de-init and flag it so
+
+From: Aradhya Bhatia <a-bhatia1@ti.com>
+
+commit fd2611c13f69cbbc6b81d9fc7502abf4f7031d21 upstream.
+
+The driver code doesn't have a Phy de-initialization path as yet, and so
+it does not clear the phy_initialized flag while suspending. This is a
+problem because after resume the driver looks at this flag to determine
+if a Phy re-initialization is required or not. It is in fact required
+because the hardware is resuming from a suspend, but the driver does not
+carry out any re-initialization causing the D-Phy to not work at all.
+
+Call the counterparts of phy_init() and phy_power_on(), that are
+phy_exit() and phy_power_off(), from _bridge_post_disable(), and clear
+the flags so that the Phy can be initialized again when required.
+
+Fixes: fced5a364dee ("drm/bridge: cdns: Convert to phy framework")
+Cc: stable@vger.kernel.org
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Tested-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
+Signed-off-by: Aradhya Bhatia <aradhya.bhatia@linux.dev>
+Link: https://lore.kernel.org/r/20250329113925.68204-3-aradhya.bhatia@linux.dev
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
++++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+@@ -681,6 +681,11 @@ static void cdns_dsi_bridge_post_disable
+ struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
+ struct cdns_dsi *dsi = input_to_dsi(input);
+
++ dsi->phy_initialized = false;
++ dsi->link_initialized = false;
++ phy_power_off(dsi->dphy);
++ phy_exit(dsi->dphy);
++
+ pm_runtime_put(dsi->base.dev);
+ }
+
+@@ -1153,7 +1158,6 @@ static int __maybe_unused cdns_dsi_suspe
+ clk_disable_unprepare(dsi->dsi_sys_clk);
+ clk_disable_unprepare(dsi->dsi_p_clk);
+ reset_control_assert(dsi->dsi_p_rst);
+- dsi->link_initialized = false;
+ return 0;
+ }
+
--- /dev/null
+From 132bdcec399be6ae947582249a134b38cf56731c Mon Sep 17 00:00:00 2001
+From: Aradhya Bhatia <a-bhatia1@ti.com>
+Date: Sat, 29 Mar 2025 17:09:14 +0530
+Subject: drm/bridge: cdns-dsi: Fix the clock variable for mode_valid()
+
+From: Aradhya Bhatia <a-bhatia1@ti.com>
+
+commit 132bdcec399be6ae947582249a134b38cf56731c upstream.
+
+The crtc_* mode parameters do not get generated (duplicated in this
+case) from the regular parameters before the mode validation phase
+begins.
+
+The rest of the code conditionally uses the crtc_* parameters only
+during the bridge enable phase, but sticks to the regular parameters
+for mode validation. In this singular instance, however, the driver
+tries to use the crtc_clock parameter even during the mode validation,
+causing the validation to fail.
+
+Allow the D-Phy config checks to use mode->clock instead of
+mode->crtc_clock during mode_valid checks, like everywhere else in the
+driver.
+
+Fixes: fced5a364dee ("drm/bridge: cdns: Convert to phy framework")
+Cc: stable@vger.kernel.org
+Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Tested-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
+Signed-off-by: Aradhya Bhatia <aradhya.bhatia@linux.dev>
+Link: https://lore.kernel.org/r/20250329113925.68204-4-aradhya.bhatia@linux.dev
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
++++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+@@ -568,13 +568,14 @@ static int cdns_dsi_check_conf(struct cd
+ struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;
+ unsigned long dsi_hss_hsa_hse_hbp;
+ unsigned int nlanes = output->dev->lanes;
++ int mode_clock = (mode_valid_check ? mode->clock : mode->crtc_clock);
+ int ret;
+
+ ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg, mode_valid_check);
+ if (ret)
+ return ret;
+
+- phy_mipi_dphy_get_default_config(mode->crtc_clock * 1000,
++ phy_mipi_dphy_get_default_config(mode_clock * 1000,
+ mipi_dsi_pixel_format_to_bpp(output->dev->format),
+ nlanes, phy_cfg);
+
--- /dev/null
+From 47c03e6660e96cbba0239125b1d4a9db3c724b1d Mon Sep 17 00:00:00 2001
+From: Aradhya Bhatia <a-bhatia1@ti.com>
+Date: Sat, 29 Mar 2025 17:09:16 +0530
+Subject: drm/bridge: cdns-dsi: Wait for Clk and Data Lanes to be ready
+
+From: Aradhya Bhatia <a-bhatia1@ti.com>
+
+commit 47c03e6660e96cbba0239125b1d4a9db3c724b1d upstream.
+
+Once the DSI Link and DSI Phy are initialized, the code needs to wait
+for Clk and Data Lanes to be ready, before continuing configuration.
+This is in accordance with the DSI Start-up procedure, found in the
+Technical Reference Manual of Texas Instrument's J721E SoC[0] which
+houses this DSI TX controller.
+
+If the previous bridge (or crtc/encoder) are configured pre-maturely,
+the input signal FIFO gets corrupt. This introduces a color-shift on the
+display.
+
+Allow the driver to wait for the clk and data lanes to get ready during
+DSI enable.
+
+[0]: See section 12.6.5.7.3 "Start-up Procedure" in J721E SoC TRM
+ TRM Link: http://www.ti.com/lit/pdf/spruil1
+
+Fixes: e19233955d9e ("drm/bridge: Add Cadence DSI driver")
+Cc: stable@vger.kernel.org
+Tested-by: Dominik Haller <d.haller@phytec.de>
+Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Tested-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
+Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
+Signed-off-by: Aradhya Bhatia <aradhya.bhatia@linux.dev>
+Link: https://lore.kernel.org/r/20250329113925.68204-6-aradhya.bhatia@linux.dev
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c | 15 ++++++++++++++-
+ 1 file changed, 14 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
++++ b/drivers/gpu/drm/bridge/cadence/cdns-dsi-core.c
+@@ -769,7 +769,7 @@ static void cdns_dsi_bridge_enable(struc
+ struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;
+ unsigned long tx_byte_period;
+ struct cdns_dsi_cfg dsi_cfg;
+- u32 tmp, reg_wakeup, div;
++ u32 tmp, reg_wakeup, div, status;
+ int nlanes;
+
+ if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
+@@ -786,6 +786,19 @@ static void cdns_dsi_bridge_enable(struc
+ cdns_dsi_hs_init(dsi);
+ cdns_dsi_init_link(dsi);
+
++ /*
++ * Now that the DSI Link and DSI Phy are initialized,
++ * wait for the CLK and Data Lanes to be ready.
++ */
++ tmp = CLK_LANE_RDY;
++ for (int i = 0; i < nlanes; i++)
++ tmp |= DATA_LANE_RDY(i);
++
++ if (readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status,
++ (tmp == (status & tmp)), 100, 500000))
++ dev_err(dsi->base.dev,
++ "Timed Out: DSI-DPhy Clock and Data Lanes not ready.\n");
++
+ writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa),
+ dsi->regs + VID_HSIZE1);
+ writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact),
--- /dev/null
+From 25eeba495b2fc16037647c1a51bcdf6fc157af5c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
+Date: Mon, 12 May 2025 21:22:15 +0200
+Subject: drm/i915/gem: Allow EXEC_CAPTURE on recoverable contexts on DG1
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Ville Syrjälä <ville.syrjala@linux.intel.com>
+
+commit 25eeba495b2fc16037647c1a51bcdf6fc157af5c upstream.
+
+The intel-media-driver is currently broken on DG1 because
+it uses EXEC_CAPTURE with recovarable contexts. Relax the
+check to allow that.
+
+I've also submitted a fix for the intel-media-driver:
+https://github.com/intel/media-driver/pull/1920
+
+Cc: stable@vger.kernel.org # v6.0+
+Cc: Matthew Auld <matthew.auld@intel.com>
+Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
+Testcase: igt/gem_exec_capture/capture-invisible
+Fixes: 71b1669ea9bd ("drm/i915/uapi: tweak error capture on recoverable contexts")
+Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
+Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
+Link: https://lore.kernel.org/r/20250411144313.11660-2-ville.syrjala@linux.intel.com
+(cherry picked from commit d6e020819612a4a06207af858e0978be4d3e3140)
+Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
++++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+@@ -2013,7 +2013,7 @@ static int eb_capture_stage(struct i915_
+ continue;
+
+ if (i915_gem_context_is_recoverable(eb->gem_context) &&
+- (IS_DGFX(eb->i915) || GRAPHICS_VER_FULL(eb->i915) > IP_VER(12, 0)))
++ GRAPHICS_VER_FULL(eb->i915) > IP_VER(12, 10))
+ return -EINVAL;
+
+ for_each_batch_create_order(eb, j) {
drm-udl-unregister-device-before-cleaning-up-on-disconnect.patch
drm-msm-gpu-fix-crash-when-throttling-gpu-immediately-during-boot.patch
drm-amdkfd-fix-race-in-gws-queue-scheduling.patch
+drm-bridge-cdns-dsi-fix-the-clock-variable-for-mode_valid.patch
+drm-bridge-cdns-dsi-fix-phy-de-init-and-flag-it-so.patch
+drm-bridge-cdns-dsi-fix-connecting-to-next-bridge.patch
+drm-bridge-cdns-dsi-check-return-value-when-getting-default-phy-config.patch
+drm-bridge-cdns-dsi-wait-for-clk-and-data-lanes-to-be-ready.patch
+drm-amd-display-add-null-pointer-check-for-get_first_active_display.patch
+drm-amdgpu-amdgpu_vram_mgr_new-clamp-lpfn-to-total-vram.patch
+drm-i915-gem-allow-exec_capture-on-recoverable-contexts-on-dg1.patch
+drm-amdgpu-add-kicker-device-detection.patch
+drm-amdgpu-switch-job-hw_fence-to-amdgpu_fence.patch
projects / thirdparty / kernel / stable-queue.git / commitdiff
