--- /dev/null
+From 2fe8ea4913493b66bd05600db9241d3cd4d5af4a Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 18 May 2022 11:08:58 +0200
+Subject: ACPI: bus: Set CPPC _OSC bits for all and when CPPC_LIB is supported
+
+From: Pierre Gondois <pierre.gondois@arm.com>
+
+[ Upstream commit 72f2ecb7ece7c1d89758d4929d98e95d95fe7199 ]
+
+The _OSC method allows the OS and firmware to communicate about
+supported features/capabitlities. It also allows the OS to take
+control of some features.
+
+In ACPI 6.4, s6.2.11.2 Platform-Wide OSPM Capabilities, the CPPC
+(resp. v2) bit should be set by the OS if it 'supports controlling
+processor performance via the interfaces described in the _CPC
+object'.
+
+The OS supports CPPC and parses the _CPC object only if
+CONFIG_ACPI_CPPC_LIB is set. Replace the x86 specific
+boot_cpu_has(X86_FEATURE_HWP) dynamic check with an arch
+generic CONFIG_ACPI_CPPC_LIB build-time check.
+
+Note:
+CONFIG_X86_INTEL_PSTATE selects CONFIG_ACPI_CPPC_LIB.
+
+Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/acpi/bus.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
+index 9eca43d1d941..1fc24f4fbcb4 100644
+--- a/drivers/acpi/bus.c
++++ b/drivers/acpi/bus.c
+@@ -329,10 +329,11 @@ static void acpi_bus_osc_negotiate_platform_control(void)
+ #endif
+ #ifdef CONFIG_X86
+ capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_GENERIC_INITIATOR_SUPPORT;
+- if (boot_cpu_has(X86_FEATURE_HWP)) {
+- capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_SUPPORT;
+- capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPCV2_SUPPORT;
+- }
++#endif
++
++#ifdef CONFIG_ACPI_CPPC_LIB
++ capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_SUPPORT;
++ capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPCV2_SUPPORT;
+ #endif
+
+ capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_FLEXIBLE_ADR_SPACE;
+@@ -357,10 +358,9 @@ static void acpi_bus_osc_negotiate_platform_control(void)
+ return;
+ }
+
+-#ifdef CONFIG_X86
+- if (boot_cpu_has(X86_FEATURE_HWP))
+- osc_sb_cppc_not_supported = !(capbuf_ret[OSC_SUPPORT_DWORD] &
+- (OSC_SB_CPC_SUPPORT | OSC_SB_CPCV2_SUPPORT));
++#ifdef CONFIG_ACPI_CPPC_LIB
++ osc_sb_cppc_not_supported = !(capbuf_ret[OSC_SUPPORT_DWORD] &
++ (OSC_SB_CPC_SUPPORT | OSC_SB_CPCV2_SUPPORT));
+ #endif
+
+ /*
+--
+2.35.1
+
--- /dev/null
+From 569af7365c3c7d4c9917cb54e5605737ff6a97a6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 18 May 2022 11:08:57 +0200
+Subject: ACPI: CPPC: Check _OSC for flexible address space
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Pierre Gondois <pierre.gondois@arm.com>
+
+[ Upstream commit 0651ab90e4ade17f1d4f4367b70f6120480410f3 ]
+
+ACPI 6.2 Section 6.2.11.2 'Platform-Wide OSPM Capabilities':
+ Starting with ACPI Specification 6.2, all _CPC registers can be in
+ PCC, System Memory, System IO, or Functional Fixed Hardware address
+ spaces. OSPM support for this more flexible register space scheme is
+ indicated by the “Flexible Address Space for CPPC Registers” _OSC bit
+
+Otherwise (cf ACPI 6.1, s8.4.7.1.1.X), _CPC registers must be in:
+- PCC or Functional Fixed Hardware address space if defined
+- SystemMemory address space (NULL register) if not defined
+
+Add the corresponding _OSC bit and check it when parsing _CPC objects.
+
+Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
+Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/acpi/bus.c | 18 ++++++++++++++++++
+ drivers/acpi/cppc_acpi.c | 9 +++++++++
+ include/linux/acpi.h | 2 ++
+ 3 files changed, 29 insertions(+)
+
+diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
+index 3e58b613a2c4..9eca43d1d941 100644
+--- a/drivers/acpi/bus.c
++++ b/drivers/acpi/bus.c
+@@ -278,6 +278,20 @@ bool osc_sb_apei_support_acked;
+ bool osc_pc_lpi_support_confirmed;
+ EXPORT_SYMBOL_GPL(osc_pc_lpi_support_confirmed);
+
++/*
++ * ACPI 6.2 Section 6.2.11.2 'Platform-Wide OSPM Capabilities':
++ * Starting with ACPI Specification 6.2, all _CPC registers can be in
++ * PCC, System Memory, System IO, or Functional Fixed Hardware address
++ * spaces. OSPM support for this more flexible register space scheme is
++ * indicated by the “Flexible Address Space for CPPC Registers” _OSC bit.
++ *
++ * Otherwise (cf ACPI 6.1, s8.4.7.1.1.X), _CPC registers must be in:
++ * - PCC or Functional Fixed Hardware address space if defined
++ * - SystemMemory address space (NULL register) if not defined
++ */
++bool osc_cpc_flexible_adr_space_confirmed;
++EXPORT_SYMBOL_GPL(osc_cpc_flexible_adr_space_confirmed);
++
+ /*
+ * ACPI 6.4 Operating System Capabilities for USB.
+ */
+@@ -321,6 +335,8 @@ static void acpi_bus_osc_negotiate_platform_control(void)
+ }
+ #endif
+
++ capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_FLEXIBLE_ADR_SPACE;
++
+ if (IS_ENABLED(CONFIG_SCHED_MC_PRIO))
+ capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_DIVERSE_HIGH_SUPPORT;
+
+@@ -366,6 +382,8 @@ static void acpi_bus_osc_negotiate_platform_control(void)
+ capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_PCLPI_SUPPORT;
+ osc_sb_native_usb4_support_confirmed =
+ capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_NATIVE_USB4_SUPPORT;
++ osc_cpc_flexible_adr_space_confirmed =
++ capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_CPC_FLEXIBLE_ADR_SPACE;
+ }
+
+ kfree(context.ret.pointer);
+diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
+index 34576ab0e2e1..840223c12540 100644
+--- a/drivers/acpi/cppc_acpi.c
++++ b/drivers/acpi/cppc_acpi.c
+@@ -746,6 +746,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
+ if (gas_t->address) {
+ void __iomem *addr;
+
++ if (!osc_cpc_flexible_adr_space_confirmed) {
++ pr_debug("Flexible address space capability not supported\n");
++ goto out_free;
++ }
++
+ addr = ioremap(gas_t->address, gas_t->bit_width/8);
+ if (!addr)
+ goto out_free;
+@@ -768,6 +773,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
+ gas_t->address);
+ goto out_free;
+ }
++ if (!osc_cpc_flexible_adr_space_confirmed) {
++ pr_debug("Flexible address space capability not supported\n");
++ goto out_free;
++ }
+ } else {
+ if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
+ /* Support only PCC, SystemMemory, SystemIO, and FFH type regs. */
+diff --git a/include/linux/acpi.h b/include/linux/acpi.h
+index d7136d13aa44..03465db16b68 100644
+--- a/include/linux/acpi.h
++++ b/include/linux/acpi.h
+@@ -574,6 +574,7 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
+ #define OSC_SB_OSLPI_SUPPORT 0x00000100
+ #define OSC_SB_CPC_DIVERSE_HIGH_SUPPORT 0x00001000
+ #define OSC_SB_GENERIC_INITIATOR_SUPPORT 0x00002000
++#define OSC_SB_CPC_FLEXIBLE_ADR_SPACE 0x00004000
+ #define OSC_SB_NATIVE_USB4_SUPPORT 0x00040000
+ #define OSC_SB_PRM_SUPPORT 0x00200000
+
+@@ -581,6 +582,7 @@ extern bool osc_sb_apei_support_acked;
+ extern bool osc_pc_lpi_support_confirmed;
+ extern bool osc_sb_native_usb4_support_confirmed;
+ extern bool osc_sb_cppc_not_supported;
++extern bool osc_cpc_flexible_adr_space_confirmed;
+
+ /* USB4 Capabilities */
+ #define OSC_USB_USB3_TUNNELING 0x00000001
+--
+2.35.1
+
--- /dev/null
+From 119915e9746c76a142be4e1c2625ee5e38f20510 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Jul 2022 13:29:15 -0500
+Subject: ACPI: CPPC: Don't require _OSC if X86_FEATURE_CPPC is supported
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+[ Upstream commit 8b356e536e69f3a4d6778ae9f0858a1beadabb1f ]
+
+commit 72f2ecb7ece7 ("ACPI: bus: Set CPPC _OSC bits for all and
+when CPPC_LIB is supported") added support for claiming to
+support CPPC in _OSC on non-Intel platforms.
+
+This unfortunately caused a regression on a vartiety of AMD
+platforms in the field because a number of AMD platforms don't set
+the `_OSC` bit 5 or 6 to indicate CPPC or CPPC v2 support.
+
+As these AMD platforms already claim CPPC support via a dedicated
+MSR from `X86_FEATURE_CPPC`, use this enable this feature rather
+than requiring the `_OSC` on platforms with a dedicated MSR.
+
+If there is additional breakage on the shared memory designs also
+missing this _OSC, additional follow up changes may be needed.
+
+Fixes: 72f2ecb7ece7 ("Set CPPC _OSC bits for all and when CPPC_LIB is supported")
+Reported-by: Perry Yuan <perry.yuan@amd.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/x86/kernel/acpi/cppc.c | 10 ++++++++++
+ drivers/acpi/cppc_acpi.c | 16 +++++++++++++++-
+ include/acpi/cppc_acpi.h | 1 +
+ 3 files changed, 26 insertions(+), 1 deletion(-)
+
+diff --git a/arch/x86/kernel/acpi/cppc.c b/arch/x86/kernel/acpi/cppc.c
+index df1644d9b3b6..3677df836e91 100644
+--- a/arch/x86/kernel/acpi/cppc.c
++++ b/arch/x86/kernel/acpi/cppc.c
+@@ -11,6 +11,16 @@
+
+ /* Refer to drivers/acpi/cppc_acpi.c for the description of functions */
+
++bool cpc_supported_by_cpu(void)
++{
++ switch (boot_cpu_data.x86_vendor) {
++ case X86_VENDOR_AMD:
++ case X86_VENDOR_HYGON:
++ return boot_cpu_has(X86_FEATURE_CPPC);
++ }
++ return false;
++}
++
+ bool cpc_ffh_supported(void)
+ {
+ return true;
+diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
+index 6aff8019047b..57ca7aa0e169 100644
+--- a/drivers/acpi/cppc_acpi.c
++++ b/drivers/acpi/cppc_acpi.c
+@@ -559,6 +559,19 @@ bool __weak cpc_ffh_supported(void)
+ return false;
+ }
+
++/**
++ * cpc_supported_by_cpu() - check if CPPC is supported by CPU
++ *
++ * Check if the architectural support for CPPC is present even
++ * if the _OSC hasn't prescribed it
++ *
++ * Return: true for supported, false for not supported
++ */
++bool __weak cpc_supported_by_cpu(void)
++{
++ return false;
++}
++
+ /**
+ * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
+ *
+@@ -668,7 +681,8 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
+
+ if (!osc_sb_cppc2_support_acked) {
+ pr_debug("CPPC v2 _OSC not acked\n");
+- return -ENODEV;
++ if (!cpc_supported_by_cpu())
++ return -ENODEV;
+ }
+
+ /* Parse the ACPI _CPC table for this CPU. */
+diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
+index 92b7ea8d8f5e..181907349b49 100644
+--- a/include/acpi/cppc_acpi.h
++++ b/include/acpi/cppc_acpi.h
+@@ -144,6 +144,7 @@ extern bool acpi_cpc_valid(void);
+ extern int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data);
+ extern unsigned int cppc_get_transition_latency(int cpu);
+ extern bool cpc_ffh_supported(void);
++extern bool cpc_supported_by_cpu(void);
+ extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
+ extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
+ #else /* !CONFIG_ACPI_CPPC_LIB */
+--
+2.35.1
+
--- /dev/null
+From e1deee68220ac234447843ead4de8f7f8dd0c605 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Jul 2022 13:29:14 -0500
+Subject: ACPI: CPPC: Only probe for _CPC if CPPC v2 is acked
+
+From: Mario Limonciello <mario.limonciello@amd.com>
+
+[ Upstream commit 7feec7430edddb87c24b0a86b08a03d0b496a755 ]
+
+Previously the kernel used to ignore whether the firmware masked CPPC
+or CPPCv2 and would just pretend that it worked.
+
+When support for the USB4 bit in _OSC was introduced from commit
+9e1f561afb ("ACPI: Execute platform _OSC also with query bit clear")
+the kernel began to look at the return when the query bit was clear.
+
+This caused regressions that were misdiagnosed and attempted to be solved
+as part of commit 2ca8e6285250 ("Revert "ACPI: Pass the same capabilities
+to the _OSC regardless of the query flag""). This caused a different
+regression where non-Intel systems weren't able to negotiate _OSC
+properly.
+
+This was reverted in commit 2ca8e6285250 ("Revert "ACPI: Pass the same
+capabilities to the _OSC regardless of the query flag"") and attempted to
+be fixed by commit c42fa24b4475 ("ACPI: bus: Avoid using CPPC if not
+supported by firmware") but the regression still returned.
+
+These systems with the regression only load support for CPPC from an SSDT
+dynamically when _OSC reports CPPC v2. Avoid the problem by not letting
+CPPC satisfy the requirement in `acpi_cppc_processor_probe`.
+
+Reported-by: CUI Hao <cuihao.leo@gmail.com>
+Reported-by: maxim.novozhilov@gmail.com
+Reported-by: lethe.tree@protonmail.com
+Reported-by: garystephenwright@gmail.com
+Reported-by: galaxyking0419@gmail.com
+Fixes: c42fa24b4475 ("ACPI: bus: Avoid using CPPC if not supported by firmware")
+Fixes: 2ca8e6285250 ("Revert "ACPI Pass the same capabilities to the _OSC regardless of the query flag"")
+Link: https://bugzilla.kernel.org/show_bug.cgi?id=213023
+Link: https://bugzilla.redhat.com/show_bug.cgi?id=2075387
+Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
+Tested-by: CUI Hao <cuihao.leo@gmail.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/acpi/bus.c | 11 +++++------
+ drivers/acpi/cppc_acpi.c | 4 +++-
+ include/linux/acpi.h | 2 +-
+ 3 files changed, 9 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
+index 1fc24f4fbcb4..6c735cfa7d43 100644
+--- a/drivers/acpi/bus.c
++++ b/drivers/acpi/bus.c
+@@ -298,7 +298,7 @@ EXPORT_SYMBOL_GPL(osc_cpc_flexible_adr_space_confirmed);
+ bool osc_sb_native_usb4_support_confirmed;
+ EXPORT_SYMBOL_GPL(osc_sb_native_usb4_support_confirmed);
+
+-bool osc_sb_cppc_not_supported;
++bool osc_sb_cppc2_support_acked;
+
+ static u8 sb_uuid_str[] = "0811B06E-4A27-44F9-8D60-3CBBC22E7B48";
+ static void acpi_bus_osc_negotiate_platform_control(void)
+@@ -358,11 +358,6 @@ static void acpi_bus_osc_negotiate_platform_control(void)
+ return;
+ }
+
+-#ifdef CONFIG_ACPI_CPPC_LIB
+- osc_sb_cppc_not_supported = !(capbuf_ret[OSC_SUPPORT_DWORD] &
+- (OSC_SB_CPC_SUPPORT | OSC_SB_CPCV2_SUPPORT));
+-#endif
+-
+ /*
+ * Now run _OSC again with query flag clear and with the caps
+ * supported by both the OS and the platform.
+@@ -376,6 +371,10 @@ static void acpi_bus_osc_negotiate_platform_control(void)
+
+ capbuf_ret = context.ret.pointer;
+ if (context.ret.length > OSC_SUPPORT_DWORD) {
++#ifdef CONFIG_ACPI_CPPC_LIB
++ osc_sb_cppc2_support_acked = capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_CPCV2_SUPPORT;
++#endif
++
+ osc_sb_apei_support_acked =
+ capbuf_ret[OSC_SUPPORT_DWORD] & OSC_SB_APEI_SUPPORT;
+ osc_pc_lpi_support_confirmed =
+diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
+index 840223c12540..6aff8019047b 100644
+--- a/drivers/acpi/cppc_acpi.c
++++ b/drivers/acpi/cppc_acpi.c
+@@ -666,8 +666,10 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
+ acpi_status status;
+ int ret = -ENODATA;
+
+- if (osc_sb_cppc_not_supported)
++ if (!osc_sb_cppc2_support_acked) {
++ pr_debug("CPPC v2 _OSC not acked\n");
+ return -ENODEV;
++ }
+
+ /* Parse the ACPI _CPC table for this CPU. */
+ status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
+diff --git a/include/linux/acpi.h b/include/linux/acpi.h
+index 03465db16b68..cf1f770208da 100644
+--- a/include/linux/acpi.h
++++ b/include/linux/acpi.h
+@@ -581,7 +581,7 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
+ extern bool osc_sb_apei_support_acked;
+ extern bool osc_pc_lpi_support_confirmed;
+ extern bool osc_sb_native_usb4_support_confirmed;
+-extern bool osc_sb_cppc_not_supported;
++extern bool osc_sb_cppc2_support_acked;
+ extern bool osc_cpc_flexible_adr_space_confirmed;
+
+ /* USB4 Capabilities */
+--
+2.35.1
+
--- /dev/null
+From 1e0f0fd03d2139d1783e7a392ac1e3bd1656225c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 16 Jun 2022 11:13:44 +0300
+Subject: ARM: at91: fix soc detection for SAM9X60 SiPs
+
+From: Mihai Sain <mihai.sain@microchip.com>
+
+[ Upstream commit 35074df65a8d8c5328a83e2eea948f7bbc8e6e08 ]
+
+Fix SoC detection for SAM9X60 SiPs:
+SAM9X60D5M
+SAM9X60D1G
+SAM9X60D6K
+
+Fixes: af3a10513cd6 ("drivers: soc: atmel: add per soc id and version match masks")
+Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20220616081344.1978664-1-claudiu.beznea@microchip.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/soc/atmel/soc.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c
+index b2d365ae0282..dae8a2e0f745 100644
+--- a/drivers/soc/atmel/soc.c
++++ b/drivers/soc/atmel/soc.c
+@@ -91,14 +91,14 @@ static const struct at91_soc socs[] __initconst = {
+ AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
+ AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
+ "sam9x60", "sam9x60"),
+- AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH,
+- AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
++ AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++ AT91_CIDR_VERSION_MASK, SAM9X60_D5M_EXID_MATCH,
+ "sam9x60 64MiB DDR2 SiP", "sam9x60"),
+- AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH,
+- AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
++ AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++ AT91_CIDR_VERSION_MASK, SAM9X60_D1G_EXID_MATCH,
+ "sam9x60 128MiB DDR2 SiP", "sam9x60"),
+- AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH,
+- AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
++ AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
++ AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
+ "sam9x60 8MiB SDRAM SiP", "sam9x60"),
+ #endif
+ #ifdef CONFIG_SOC_SAMA5
+--
+2.35.1
+
--- /dev/null
+From 495085c56d7b7b583e12138a87c87286f10dc28e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 23 May 2022 12:24:19 +0300
+Subject: ARM: at91: pm: use proper compatible for sama5d2's rtc
+
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+
+[ Upstream commit ddc980da8043779119acaca106c6d9b445c9b65b ]
+
+Use proper compatible strings for SAMA5D2's RTC IPs. This is necessary
+for configuring wakeup sources for ULP1 PM mode.
+
+Fixes: d7484f5c6b3b ("ARM: at91: pm: configure wakeup sources for ULP1 mode")
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20220523092421.317345-2-claudiu.beznea@microchip.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mach-at91/pm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
+index 0fd609e26615..0da13a7afa31 100644
+--- a/arch/arm/mach-at91/pm.c
++++ b/arch/arm/mach-at91/pm.c
+@@ -146,7 +146,7 @@ static const struct wakeup_source_info ws_info[] = {
+
+ static const struct of_device_id sama5d2_ws_ids[] = {
+ { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
+- { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
++ { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
+ { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
+ { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
+ { .compatible = "usb-ohci", .data = &ws_info[2] },
+--
+2.35.1
+
--- /dev/null
+From 1e693b2eb191d1463964d57faff1d1b560a6f6b5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 23 May 2022 12:24:20 +0300
+Subject: ARM: at91: pm: use proper compatibles for sam9x60's rtc and rtt
+
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+
+[ Upstream commit 641522665dbb25ce117c78746df1aad8b58c80e5 ]
+
+Use proper compatible strings for SAM9X60's RTC and RTT IPs. These are
+necessary for configuring wakeup sources for ULP1 PM mode.
+
+Fixes: eaedc0d379da ("ARM: at91: pm: add ULP1 support for SAM9X60")
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20220523092421.317345-3-claudiu.beznea@microchip.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mach-at91/pm.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
+index 0da13a7afa31..464b7dea5bbe 100644
+--- a/arch/arm/mach-at91/pm.c
++++ b/arch/arm/mach-at91/pm.c
+@@ -157,12 +157,12 @@ static const struct of_device_id sama5d2_ws_ids[] = {
+ };
+
+ static const struct of_device_id sam9x60_ws_ids[] = {
+- { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
++ { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
+ { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
+ { .compatible = "usb-ohci", .data = &ws_info[2] },
+ { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
+ { .compatible = "usb-ehci", .data = &ws_info[2] },
+- { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
++ { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
+ { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
+ { /* sentinel */ }
+ };
+--
+2.35.1
+
--- /dev/null
+From f6e0c5e5ceb18689e56ab55b2148bd311039dd0c Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 23 May 2022 12:24:21 +0300
+Subject: ARM: at91: pm: use proper compatibles for sama7g5's rtc and rtt
+
+From: Claudiu Beznea <claudiu.beznea@microchip.com>
+
+[ Upstream commit 1c40169b35ad58906814d53a517ac92db3d20d5f ]
+
+Use proper compatible strings for SAMA7G5's RTC and RTT IPs. These are
+necessary for configuring wakeup sources for ULP1 PM mode.
+
+Fixes: 6501330f9f5e ("ARM: at91: pm: add pm support for SAMA7G5")
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20220523092421.317345-4-claudiu.beznea@microchip.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mach-at91/pm.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
+index 464b7dea5bbe..32f224f723a5 100644
+--- a/arch/arm/mach-at91/pm.c
++++ b/arch/arm/mach-at91/pm.c
+@@ -168,13 +168,13 @@ static const struct of_device_id sam9x60_ws_ids[] = {
+ };
+
+ static const struct of_device_id sama7g5_ws_ids[] = {
+- { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
++ { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
+ { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
+ { .compatible = "usb-ohci", .data = &ws_info[2] },
+ { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
+ { .compatible = "usb-ehci", .data = &ws_info[2] },
+ { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
+- { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
++ { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
+ { /* sentinel */ }
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 7e1b1b350f38de8f846037de29c1435e613aeac4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 7 Jun 2022 12:04:54 +0300
+Subject: ARM: dts: at91: sam9x60ek: fix eeprom compatible and size
+
+From: Eugen Hristev <eugen.hristev@microchip.com>
+
+[ Upstream commit f2cbbc3f926316ccf8ef9363d8a60c1110afc1c7 ]
+
+The board has a microchip 24aa025e48 eeprom, which is a 2 Kbits memory,
+so it's compatible with at24c02 not at24c32.
+Also the size property is wrong, it's not 128 bytes, but 256 bytes.
+Thus removing and leaving it to the default (256).
+
+Fixes: 1e5f532c27371 ("ARM: dts: at91: sam9x60: add device tree for soc and board")
+Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
+Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20220607090455.80433-1-eugen.hristev@microchip.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/at91-sam9x60ek.dts | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts
+index 7719ea3d4933..81ccb0636a00 100644
+--- a/arch/arm/boot/dts/at91-sam9x60ek.dts
++++ b/arch/arm/boot/dts/at91-sam9x60ek.dts
+@@ -233,10 +233,9 @@
+ status = "okay";
+
+ eeprom@53 {
+- compatible = "atmel,24c32";
++ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+- size = <128>;
+ status = "okay";
+ };
+ };
+--
+2.35.1
+
--- /dev/null
+From da23b04302a312dd356a81cdbc870018129e69f1 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 7 Jun 2022 12:04:55 +0300
+Subject: ARM: dts: at91: sama5d2_icp: fix eeprom compatibles
+
+From: Eugen Hristev <eugen.hristev@microchip.com>
+
+[ Upstream commit 416ce193d73a734ded6d09fe141017b38af1c567 ]
+
+The eeprom memories on the board are microchip 24aa025e48, which are 2 Kbits
+and are compatible with at24c02 not at24c32.
+
+Fixes: 68a95ef72cefe ("ARM: dts: at91: sama5d2-icp: add SAMA5D2-ICP")
+Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
+Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
+Link: https://lore.kernel.org/r/20220607090455.80433-2-eugen.hristev@microchip.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/at91-sama5d2_icp.dts | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
+index 806eb1d911d7..164201a8fbf2 100644
+--- a/arch/arm/boot/dts/at91-sama5d2_icp.dts
++++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
+@@ -329,21 +329,21 @@
+ status = "okay";
+
+ eeprom@50 {
+- compatible = "atmel,24c32";
++ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ status = "okay";
+ };
+
+ eeprom@52 {
+- compatible = "atmel,24c32";
++ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ status = "disabled";
+ };
+
+ eeprom@53 {
+- compatible = "atmel,24c32";
++ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ status = "disabled";
+--
+2.35.1
+
--- /dev/null
+From b34ac2ca8fba10a875d54f62ffc128613f041cbf Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 21 Jun 2022 10:45:09 +0200
+Subject: ARM: dts: stm32: add missing usbh clock and fix clk order on
+ stm32mp15
+
+From: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+
+[ Upstream commit 1d0c1aadf1fd9f3de95d1532b3651e8634546e71 ]
+
+The USBH composed of EHCI and OHCI controllers needs the PHY clock to be
+initialized first, before enabling (gating) them. The reverse is also
+required when going to suspend.
+So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL
+gets enabled 1st upon controller init. Upon suspend/resume, this also makes
+the clock to be disabled/re-enabled in the correct order.
+This fixes some IRQ storm conditions seen when going to low-power, due to
+PHY PLL being disabled before all clocks are cleanly gated.
+
+Fixes: 949a0c0dec85 ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c")
+Fixes: db7be2cb87ae ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151")
+Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
+Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/boot/dts/stm32mp151.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi
+index f9aa9af31efd..9c2bbf115f4c 100644
+--- a/arch/arm/boot/dts/stm32mp151.dtsi
++++ b/arch/arm/boot/dts/stm32mp151.dtsi
+@@ -1474,7 +1474,7 @@
+ usbh_ohci: usb@5800c000 {
+ compatible = "generic-ohci";
+ reg = <0x5800c000 0x1000>;
+- clocks = <&rcc USBH>, <&usbphyc>;
++ clocks = <&usbphyc>, <&rcc USBH>;
+ resets = <&rcc USBH_R>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+@@ -1483,7 +1483,7 @@
+ usbh_ehci: usb@5800d000 {
+ compatible = "generic-ehci";
+ reg = <0x5800d000 0x1000>;
+- clocks = <&rcc USBH>;
++ clocks = <&usbphyc>, <&rcc USBH>;
+ resets = <&rcc USBH_R>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ companion = <&usbh_ohci>;
+--
+2.35.1
+
--- /dev/null
+From 8b53e1cafba8db5f9dae5e9c442bfa6b4feceba8 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 12 May 2022 06:16:10 +0400
+Subject: ARM: meson: Fix refcount leak in meson_smp_prepare_cpus
+
+From: Miaoqian Lin <linmq006@gmail.com>
+
+[ Upstream commit 34d2cd3fccced12b958b8848e3eff0ee4296764c ]
+
+of_find_compatible_node() returns a node pointer with refcount
+incremented, we should use of_node_put() on it when done.
+Add missing of_node_put() to avoid refcount leak.
+
+Fixes: d850f3e5d296 ("ARM: meson: Add SMP bringup code for Meson8 and Meson8b")
+Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
+Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+Link: https://lore.kernel.org/r/20220512021611.47921-1-linmq006@gmail.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/mach-meson/platsmp.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c
+index 4b8ad728bb42..32ac60b89fdc 100644
+--- a/arch/arm/mach-meson/platsmp.c
++++ b/arch/arm/mach-meson/platsmp.c
+@@ -71,6 +71,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible,
+ }
+
+ sram_base = of_iomap(node, 0);
++ of_node_put(node);
+ if (!sram_base) {
+ pr_err("Couldn't map SRAM registers\n");
+ return;
+@@ -91,6 +92,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible,
+ }
+
+ scu_base = of_iomap(node, 0);
++ of_node_put(node);
+ if (!scu_base) {
+ pr_err("Couldn't map SCU registers\n");
+ return;
+--
+2.35.1
+
--- /dev/null
+From 14c89c8f2588d0f3a6038d9804b76138199231dc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 21 Jun 2022 13:45:05 -0300
+Subject: ARM: mxs_defconfig: Enable the framebuffer
+
+From: Fabio Estevam <festevam@denx.de>
+
+[ Upstream commit b10ef5f2ddb3a5a22ac0936c8d91a50ac5e55e77 ]
+
+Currently, when booting Linux on a imx28-evk board there is
+no display activity.
+
+Enable CONFIG_FB which is nowadays required for CONFIG_DRM_PANEL_LVDS,
+CONFIG_DRM_PANEL_SIMPLE, CONFIG_DRM_PANEL_SEIKO_43WVF1G,
+CONFIG_FB_MODE_HELPERS, CONFIG_BACKLIGHT_PWM, CONFIG_BACKLIGHT_GPIO,
+CONFIG_FRAMEBUFFER_CONSOLE, CONFIG_LOGO, CONFIG_FONTS, CONFIG_FONT_8x8
+and CONFIG_FONT_8x16.
+
+Based on commit c54467482ffd ("ARM: imx_v6_v7_defconfig: enable fb").
+
+Fixes: f611b1e7624c ("drm: Avoid circular dependencies for CONFIG_FB")
+Signed-off-by: Fabio Estevam <festevam@denx.de>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm/configs/mxs_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
+index ca32446b187f..f53086ddc48b 100644
+--- a/arch/arm/configs/mxs_defconfig
++++ b/arch/arm/configs/mxs_defconfig
+@@ -93,6 +93,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
+ CONFIG_DRM=y
+ CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
+ CONFIG_DRM_MXSFB=y
++CONFIG_FB=y
+ CONFIG_FB_MODE_HELPERS=y
+ CONFIG_LCD_CLASS_DEVICE=y
+ CONFIG_BACKLIGHT_CLASS_DEVICE=y
+--
+2.35.1
+
--- /dev/null
+From 50d5e52b486c0ca4cfea3f2a11b23c3191e668c7 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:14:01 +0800
+Subject: arm64: dts: imx8mp-evk: correct eqos pad settings
+
+From: Peng Fan <peng.fan@nxp.com>
+
+[ Upstream commit e6e1bc0ec9e8ad212fa46d8878a6e17cd31fdf7b ]
+
+According to RM bit layout, BIT3 and BIT0 are reserved.
+ 8 7 6 5 4 3 2 1 0
+PE HYS PUE ODE FSEL X DSE X
+
+Although function is not broken, we should not set reserved bit.
+
+Fixes: dc6d5dc89bad ("arm64: dts: imx8mp-evk: enable EQOS ethernet")
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 30 ++++++++++----------
+ 1 file changed, 15 insertions(+), 15 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+index a28ce8af61bd..454856bd4f56 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+@@ -395,21 +395,21 @@
+ &iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+- MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
++ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
++ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
++ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
++ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
++ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
++ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
++ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
++ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
++ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
++ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
++ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
++ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
++ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
++ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
++ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
+ >;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From efb7fd4d112343bdb213741e3f6d2d176e52c375 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:13:59 +0800
+Subject: arm64: dts: imx8mp-evk: correct gpio-led pad settings
+
+From: Peng Fan <peng.fan@nxp.com>
+
+[ Upstream commit b838582ab8d5fb11b2c0275056a9f34e1d94fece ]
+
+0x19 is not a valid setting. According to RM bit layout,
+BIT3 and BIT0 are reserved.
+ 8 7 6 5 4 3 2 1 0
+ PE HYS PUE ODE FSEL X DSE X
+
+Correct setting with PE PUE set, DSE set to 0.
+
+Fixes: 50d336b12f34 ("arm64: dts: imx8mp-evk: Add GPIO LED support")
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+index 4ba31fc5d0a5..4ff75c4cbddc 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+@@ -461,7 +461,7 @@
+
+ pinctrl_gpio_led: gpioledgrp {
+ fsl,pins = <
+- MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
++ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
+ >;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From a3b85e939423e9ffb180127840e88cca261bfcb3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:14:04 +0800
+Subject: arm64: dts: imx8mp-evk: correct I2C1 pad settings
+
+From: Peng Fan <peng.fan@nxp.com>
+
+[ Upstream commit 05a7f43478e890513d571f36660bfedc1482a588 ]
+
+According to RM bit layout, BIT3 and BIT0 are reserved.
+ 8 7 6 5 4 3 2 1 0
+PE HYS PUE ODE FSEL X DSE X
+
+Although function is not broken, we should not set reserved bit.
+
+Fixes: 5497bc2a2bff ("arm64: dts: imx8mp-evk: Add PMIC device")
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+index 938757b26add..b4499d9953ed 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+@@ -467,8 +467,8 @@
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+- MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+- MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
++ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
++ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
+ >;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 4e8b53c0afd3c5dc57a5dcbeee1d56aac32a0117 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:14:05 +0800
+Subject: arm64: dts: imx8mp-evk: correct I2C3 pad settings
+
+From: Peng Fan <peng.fan@nxp.com>
+
+[ Upstream commit 0836de513ebaae5f03014641eac996290d67493d ]
+
+According to RM bit layout, BIT3 and BIT0 are reserved.
+ 8 7 6 5 4 3 2 1 0
+PE HYS PUE ODE FSEL X DSE X
+
+Although function is not broken, we should not set reserved bit.
+
+Fixes: 5e4a67ff7f69 ("arm64: dts: imx8mp-evk: Add i2c3 support")
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+index b4499d9953ed..5744fa76e9b2 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+@@ -474,8 +474,8 @@
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+- MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
+- MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
++ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
++ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
+ >;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From c591443ce4ea3cdcbc475d395b87386b95c71504 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:14:03 +0800
+Subject: arm64: dts: imx8mp-evk: correct I2C5 pad settings
+
+From: Peng Fan <peng.fan@nxp.com>
+
+[ Upstream commit 8c214b78e149dc7209e38a031292fe21d7017561 ]
+
+According to RM bit layout, BIT3 and BIT0 are reserved.
+ 8 7 6 5 4 3 2 1 0
+PE HYS PUE ODE FSEL X DSE X
+
+Although function is not broken, we should not set reserved bit.
+
+Fixes: 8134822db08d ("arm64: dts: imx8mp-evk: add support for I2C5")
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+index 454856bd4f56..938757b26add 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+@@ -481,8 +481,8 @@
+
+ pinctrl_i2c5: i2c5grp {
+ fsl,pins = <
+- MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3
+- MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3
++ MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
++ MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
+ >;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From c385a77a69ce3e53ec5aee31cec0c201c6e737fc Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:13:57 +0800
+Subject: arm64: dts: imx8mp-evk: correct mmc pad settings
+
+From: Peng Fan <peng.fan@nxp.com>
+
+[ Upstream commit 01785f1f156511c4f285786b4192245d4f476bf1 ]
+
+According to RM bit layout, BIT3 and BIT0 are reserved.
+ 8 7 6 5 4 3 2 1 0
+ PE HYS PUE ODE FSEL X DSE X
+
+Not set reserved bit.
+
+Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support")
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+index 4c3ac4214a2c..f31cf778890d 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+@@ -500,7 +500,7 @@
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
++ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
+ >;
+ };
+
+@@ -525,7 +525,7 @@
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
+ >;
+ };
+
+@@ -537,7 +537,7 @@
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
+ >;
+ };
+
+@@ -549,7 +549,7 @@
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
+ >;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 72696637dc6a855522aee91fbd516dd9c15f132d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:13:58 +0800
+Subject: arm64: dts: imx8mp-evk: correct the uart2 pinctl value
+
+From: Sherry Sun <sherry.sun@nxp.com>
+
+[ Upstream commit 2d4fb72b681205eed4553d8802632bd3270be3ba ]
+
+According to the IOMUXC_SW_PAD_CTL_PAD_UART2_RXD/TXD register define in
+imx8mp RM, bit0 and bit3 are reserved, and the uart2 rx/tx pin should
+enable the pull up, so need to set bit8 to 1. The original pinctl value
+0x49 is incorrect and needs to be changed to 0x140, same as uart1 and
+uart3.
+
+Fixes: 9e847693c6f3 ("arm64: dts: freescale: Add i.MX8MP EVK board support")
+Reviewed-by: Haibo Chen <haibo.chen@nxp.com>
+Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+index f31cf778890d..4ba31fc5d0a5 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+@@ -506,8 +506,8 @@
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+- MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
+- MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
++ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
++ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
+ >;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From bc1a4b109a688ddb3b0e7e9e313552fdfda6dc5d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:14:00 +0800
+Subject: arm64: dts: imx8mp-evk: correct vbus pad settings
+
+From: Peng Fan <peng.fan@nxp.com>
+
+[ Upstream commit e2c00820a99c55c9bb40642d5818a904a1e0d664 ]
+
+0x19 is not a valid setting. According to RM bit layout, BIT3 and BIT0
+are reserved.
+ 8 7 6 5 4 3 2 1 0
+ PE HYS PUE ODE FSEL X DSE X
+
+Not set reserved bit.
+
+Fixes: 43da4f92a611 ("arm64: dts: imx8mp-evk: enable usb1 as host mode")
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+index 4ff75c4cbddc..a28ce8af61bd 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+@@ -513,7 +513,7 @@
+
+ pinctrl_usb1_vbus: usb1grp {
+ fsl,pins = <
+- MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19
++ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
+ >;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From c1cfa461e9710e3f01cee2ec7122c0433386d6c0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:14:08 +0800
+Subject: arm64: dts: imx8mp-phyboard-pollux-rdk: correct eqos pad settings
+
+From: Peng Fan <peng.fan@nxp.com>
+
+[ Upstream commit bae4de618efe1c41d34aa2e6cef8b08e46256667 ]
+
+BIT3 and BIT0 are reserved bits, should not touch.
+
+Fixes: 6f96852619d5 ("arm64: dts: freescale: Add support EQOS MAC on phyBOARD-Pollux-i.MX8MP")
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../freescale/imx8mp-phyboard-pollux-rdk.dts | 28 +++++++++----------
+ 1 file changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+index e34076954897..cefd3d36f93f 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+@@ -116,20 +116,20 @@
+ &iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+- MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+- MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+- MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+- MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+- MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+- MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+- MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+- MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+- MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+- MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+- MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+- MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+- MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+- MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
++ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
++ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
++ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
++ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
++ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
++ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
++ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
++ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
++ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
++ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
++ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
++ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
++ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
++ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
+ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
+ >;
+ };
+--
+2.35.1
+
--- /dev/null
+From d619473a59761bb21f2472d68791bcc35b5b12fa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:14:09 +0800
+Subject: arm64: dts: imx8mp-phyboard-pollux-rdk: correct i2c2 & mmc settings
+
+From: Peng Fan <peng.fan@nxp.com>
+
+[ Upstream commit 242d8ee9111171a6e68249aaff62643c513be6ec ]
+
+BIT3 and BIT0 are reserved bits, should not touch.
+
+Fixes: 88f7f6bcca37 ("arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP")
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+index cefd3d36f93f..6aa720bafe28 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+@@ -136,21 +136,21 @@
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+- MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
+- MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
++ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
++ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2gpiogrp {
+ fsl,pins = <
+- MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3
+- MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3
++ MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
++ MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+- MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
++ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
+ >;
+ };
+
+@@ -175,7 +175,7 @@
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
+- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
+ >;
+ };
+
+@@ -187,7 +187,7 @@
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
+- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
+ >;
+ };
+
+@@ -199,7 +199,7 @@
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
+- MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
++ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
+ >;
+ };
+ };
+--
+2.35.1
+
--- /dev/null
+From 6db328544cf6f7a4ef88ea2e5b3921a27434989e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 14:14:07 +0800
+Subject: arm64: dts: imx8mp-phyboard-pollux-rdk: correct uart pad settings
+
+From: Peng Fan <peng.fan@nxp.com>
+
+[ Upstream commit e266c155bd88e95f9b86379d6b0add6ac6e5452e ]
+
+BIT3 and BIT0 are reserved bits, should not touch.
+
+Fixes: 846f752866bd ("arm64: dts: imx8mp-phyboard-pollux-rdk: Change debug UART")
+Signed-off-by: Peng Fan <peng.fan@nxp.com>
+Reviewed-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+index 984a6b9ded8d..e34076954897 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+@@ -156,8 +156,8 @@
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+- MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49
+- MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49
++ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
++ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
+ >;
+ };
+
+--
+2.35.1
+
--- /dev/null
+From 729043a740c4e488cfe668242f59160eeee5f715 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 27 Jun 2022 15:59:38 +0200
+Subject: arm64: dts: qcom: msm8992-*: Fix vdd_lvs1_2-supply typo
+
+From: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
+
+[ Upstream commit 5fb779558f1c97e2bf2794cb59553e569c38e2f9 ]
+
+"make dtbs_check" complains about the missing "-supply" suffix for
+vdd_lvs1_2 which is clearly a typo, originally introduced in the
+msm8994-smd-rpm.dtsi file and apparently later copied to
+msm8992-xiaomi-libra.dts:
+
+msm8992-lg-bullhead-rev-10/101.dtb: pm8994-regulators: 'vdd_lvs1_2'
+does not match any of the regexes:
+ '.*-supply$', '^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$', 'pinctrl-[0-9]+'
+From schema: regulator/qcom,smd-rpm-regulator.yaml
+
+msm8992-xiaomi-libra.dtb: pm8994-regulators: 'vdd_lvs1_2'
+does not match any of the regexes:
+ '.*-supply$', '^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$', 'pinctrl-[0-9]+'
+From schema: regulator/qcom,smd-rpm-regulator.yaml
+
+Reported-by: Rob Herring <robh@kernel.org>
+Cc: Konrad Dybcio <konrad.dybcio@somainline.org>
+Fixes: f3b2c99e73be ("arm64: dts: Enable onboard SDHCI on msm8992")
+Fixes: 0f5cdb31e850 ("arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device tree")
+Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220627135938.2901871-1-stephan.gerhold@kernkonzept.com
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi | 2 +-
+ arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
+index 3b0cc85d6674..71e373b11de9 100644
+--- a/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
++++ b/arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
+@@ -74,7 +74,7 @@
+ vdd_l17_29-supply = <&vph_pwr>;
+ vdd_l20_21-supply = <&vph_pwr>;
+ vdd_l25-supply = <&pm8994_s5>;
+- vdd_lvs1_2 = <&pm8994_s4>;
++ vdd_lvs1_2-supply = <&pm8994_s4>;
+
+ /* S1, S2, S6 and S12 are managed by RPMPD */
+
+diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
+index 84558ab5fe86..ae882bfbf48d 100644
+--- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
++++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
+@@ -143,7 +143,7 @@
+ vdd_l17_29-supply = <&vph_pwr>;
+ vdd_l20_21-supply = <&vph_pwr>;
+ vdd_l25-supply = <&pm8994_s5>;
+- vdd_lvs1_2 = <&pm8994_s4>;
++ vdd_lvs1_2-supply = <&pm8994_s4>;
+
+ /* S1, S2, S6 and S12 are managed by RPMPD */
+
+--
+2.35.1
+
--- /dev/null
+From 2aec69cef4976a1dd5135d57b05d415037635558 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 1 May 2022 20:40:16 +0200
+Subject: arm64: dts: qcom: msm8994: Fix CPU6/7 reg values
+
+From: Konrad Dybcio <konrad.dybcio@somainline.org>
+
+[ Upstream commit 47bf59c4755930f616dd90c8c6a85f40a6d347ea ]
+
+CPU6 and CPU7 were mistakengly pointing to CPU5 reg. Fix it.
+
+Fixes: 02d8091bbca0 ("arm64: dts: qcom: msm8994: Add a proper CPU map")
+Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220501184016.64138-1-konrad.dybcio@somainline.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
+index b1e595cb4b90..6b76321288d0 100644
+--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
++++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
+@@ -93,7 +93,7 @@
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+- reg = <0x0 0x101>;
++ reg = <0x0 0x102>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ };
+@@ -101,7 +101,7 @@
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+- reg = <0x0 0x101>;
++ reg = <0x0 0x103>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ };
+--
+2.35.1
+
--- /dev/null
+From 2a3722686e092393dd59f310a65b5bd13ce1b1ae Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 31 May 2022 15:47:35 +0300
+Subject: arm64: dts: qcom: sdm845: use dispcc AHB clock for mdss node
+
+From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+
+[ Upstream commit 3ba500dee327e0261e728edec8a4f2f563d2760c ]
+
+It was noticed that on sdm845 after an MDSS suspend/resume cycle the
+driver can not read HW_REV registers properly (they will return 0
+instead). Chaning the "iface" clock from <&gcc GCC_DISP_AHB_CLK> to
+<&dispcc DISP_CC_MDSS_AHB_CLK> fixes the issue.
+
+Fixes: 08c2a076d18f ("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file")
+Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220531124735.1165582-1-dmitry.baryshkov@linaro.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
+index b31bf62e8680..ad21cf465c98 100644
+--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
++++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
+@@ -4238,7 +4238,7 @@
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+- clocks = <&gcc GCC_DISP_AHB_CLK>,
++ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "core";
+
+--
+2.35.1
+
--- /dev/null
+From c778de3c7258e9a209f0978b6a24384d979441d3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 11 Mar 2022 00:19:34 +0200
+Subject: arm64: dts: qcom: sm8450: fix interconnects property of UFS node
+
+From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
+
+[ Upstream commit de9b3d9616078f1d1d0d51b01cdafa101733f935 ]
+
+All interconnect device tree nodes on sm8450 are 2-cells, however in
+UFS node they are handled as 1-cells, fix it.
+
+Fixes: aa2d0bf04a3c ("arm64: dts: qcom: sm8450: add interconnect nodes")
+Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+Link: https://lore.kernel.org/r/20220310221934.1560729-1-vladimir.zapolskiy@linaro.org
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
+index e63b7b0458cf..7a14eb89e4ca 100644
+--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
++++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
+@@ -1383,8 +1383,8 @@
+
+ iommus = <&apps_smmu 0xe0 0x0>;
+
+- interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
+- <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
++ interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
++ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
+ interconnect-names = "ufs-ddr", "cpu-ufs";
+ clock-names =
+ "core_clk",
+--
+2.35.1
+
--- /dev/null
+From 8d78041074a715cef6e1e2a6f27c7c402b6778aa Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 6 Jun 2022 15:37:52 -0500
+Subject: ASoC: codecs: rt700/rt711/rt711-sdca: resume bus/codec in
+ .set_jack_detect
+
+From: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+
+[ Upstream commit 40737057b48f1b4db67b0d766b95c87ba8fc5e03 ]
+
+The .set_jack_detect() codec component callback is invoked during card
+registration, which happens when the machine driver is probed.
+
+The issue is that this callback can race with the bus suspend/resume,
+and IO timeouts can happen. This can be reproduced very easily if the
+machine driver is 'blacklisted' and manually probed after the bus
+suspends. The bus and codec need to be re-initialized using pm_runtime
+helpers.
+
+Previous contributions tried to make sure accesses to the bus during
+the .set_jack_detect() component callback only happen when the bus is
+active. This was done by changing the regcache status on a component
+remove. This is however a layering violation, the regcache status
+should only be modified on device probe, suspend and resume. The
+component probe/remove should not modify how the device regcache is
+handled. This solution also didn't handle all the possible race
+conditions, and the RT700 headset codec was not handled.
+
+This patch tries to resume the codec device before handling the jack
+initializations. In case the codec has not yet been initialized,
+pm_runtime may not be enabled yet, so we don't squelch the -EACCES
+error code and only stop the jack information. When the codec reports
+as attached, the jack initialization will proceed as usual.
+
+BugLink: https://github.com/thesofproject/linux/issues/3643
+Fixes: 7ad4d237e7c4a ('ASoC: rt711-sdca: Add RT711 SDCA vendor-specific driver')
+Fixes: 899b12542b089 ('ASoC: rt711: add snd_soc_component remove callback')
+Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+Reviewed-by: Rander Wang <rander.wang@intel.com>
+Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
+Link: https://lore.kernel.org/r/20220606203752.144159-8-pierre-louis.bossart@linux.intel.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/rt700.c | 16 +++++++++++++---
+ sound/soc/codecs/rt711-sdca.c | 26 ++++++++++++++------------
+ sound/soc/codecs/rt711.c | 24 +++++++++++++-----------
+ 3 files changed, 40 insertions(+), 26 deletions(-)
+
+diff --git a/sound/soc/codecs/rt700.c b/sound/soc/codecs/rt700.c
+index e61a8257bf64..360d61a36c35 100644
+--- a/sound/soc/codecs/rt700.c
++++ b/sound/soc/codecs/rt700.c
+@@ -315,17 +315,27 @@ static int rt700_set_jack_detect(struct snd_soc_component *component,
+ struct snd_soc_jack *hs_jack, void *data)
+ {
+ struct rt700_priv *rt700 = snd_soc_component_get_drvdata(component);
++ int ret;
+
+ rt700->hs_jack = hs_jack;
+
+- if (!rt700->hw_init) {
+- dev_dbg(&rt700->slave->dev,
+- "%s hw_init not ready yet\n", __func__);
++ ret = pm_runtime_resume_and_get(component->dev);
++ if (ret < 0) {
++ if (ret != -EACCES) {
++ dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
++ return ret;
++ }
++
++ /* pm_runtime not enabled yet */
++ dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
+ return 0;
+ }
+
+ rt700_jack_init(rt700);
+
++ pm_runtime_mark_last_busy(component->dev);
++ pm_runtime_put_autosuspend(component->dev);
++
+ return 0;
+ }
+
+diff --git a/sound/soc/codecs/rt711-sdca.c b/sound/soc/codecs/rt711-sdca.c
+index 57629c18db38..9d59e653b941 100644
+--- a/sound/soc/codecs/rt711-sdca.c
++++ b/sound/soc/codecs/rt711-sdca.c
+@@ -487,16 +487,27 @@ static int rt711_sdca_set_jack_detect(struct snd_soc_component *component,
+ struct snd_soc_jack *hs_jack, void *data)
+ {
+ struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
++ int ret;
+
+ rt711->hs_jack = hs_jack;
+
+- if (!rt711->hw_init) {
+- dev_dbg(&rt711->slave->dev,
+- "%s hw_init not ready yet\n", __func__);
++ ret = pm_runtime_resume_and_get(component->dev);
++ if (ret < 0) {
++ if (ret != -EACCES) {
++ dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
++ return ret;
++ }
++
++ /* pm_runtime not enabled yet */
++ dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
+ return 0;
+ }
+
+ rt711_sdca_jack_init(rt711);
++
++ pm_runtime_mark_last_busy(component->dev);
++ pm_runtime_put_autosuspend(component->dev);
++
+ return 0;
+ }
+
+@@ -1190,14 +1201,6 @@ static int rt711_sdca_probe(struct snd_soc_component *component)
+ return 0;
+ }
+
+-static void rt711_sdca_remove(struct snd_soc_component *component)
+-{
+- struct rt711_sdca_priv *rt711 = snd_soc_component_get_drvdata(component);
+-
+- regcache_cache_only(rt711->regmap, true);
+- regcache_cache_only(rt711->mbq_regmap, true);
+-}
+-
+ static const struct snd_soc_component_driver soc_sdca_dev_rt711 = {
+ .probe = rt711_sdca_probe,
+ .controls = rt711_sdca_snd_controls,
+@@ -1207,7 +1210,6 @@ static const struct snd_soc_component_driver soc_sdca_dev_rt711 = {
+ .dapm_routes = rt711_sdca_audio_map,
+ .num_dapm_routes = ARRAY_SIZE(rt711_sdca_audio_map),
+ .set_jack = rt711_sdca_set_jack_detect,
+- .remove = rt711_sdca_remove,
+ .endianness = 1,
+ };
+
+diff --git a/sound/soc/codecs/rt711.c b/sound/soc/codecs/rt711.c
+index 9838fb4d5b9c..9958067e80f1 100644
+--- a/sound/soc/codecs/rt711.c
++++ b/sound/soc/codecs/rt711.c
+@@ -457,17 +457,27 @@ static int rt711_set_jack_detect(struct snd_soc_component *component,
+ struct snd_soc_jack *hs_jack, void *data)
+ {
+ struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
++ int ret;
+
+ rt711->hs_jack = hs_jack;
+
+- if (!rt711->hw_init) {
+- dev_dbg(&rt711->slave->dev,
+- "%s hw_init not ready yet\n", __func__);
++ ret = pm_runtime_resume_and_get(component->dev);
++ if (ret < 0) {
++ if (ret != -EACCES) {
++ dev_err(component->dev, "%s: failed to resume %d\n", __func__, ret);
++ return ret;
++ }
++
++ /* pm_runtime not enabled yet */
++ dev_dbg(component->dev, "%s: skipping jack init for now\n", __func__);
+ return 0;
+ }
+
+ rt711_jack_init(rt711);
+
++ pm_runtime_mark_last_busy(component->dev);
++ pm_runtime_put_autosuspend(component->dev);
++
+ return 0;
+ }
+
+@@ -932,13 +942,6 @@ static int rt711_probe(struct snd_soc_component *component)
+ return 0;
+ }
+
+-static void rt711_remove(struct snd_soc_component *component)
+-{
+- struct rt711_priv *rt711 = snd_soc_component_get_drvdata(component);
+-
+- regcache_cache_only(rt711->regmap, true);
+-}
+-
+ static const struct snd_soc_component_driver soc_codec_dev_rt711 = {
+ .probe = rt711_probe,
+ .set_bias_level = rt711_set_bias_level,
+@@ -949,7 +952,6 @@ static const struct snd_soc_component_driver soc_codec_dev_rt711 = {
+ .dapm_routes = rt711_audio_map,
+ .num_dapm_routes = ARRAY_SIZE(rt711_audio_map),
+ .set_jack = rt711_set_jack_detect,
+- .remove = rt711_remove,
+ .endianness = 1,
+ };
+
+--
+2.35.1
+
--- /dev/null
+From d42bbeccfc7a9610da973be07f0c230f4b1a4e60 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 4 May 2022 18:08:57 +0100
+Subject: ASoC: rt711: Add endianness flag in snd_soc_component_driver
+
+From: Charles Keepax <ckeepax@opensource.cirrus.com>
+
+[ Upstream commit 33f06beac3ade10834a82ad4105dcd91d4b00d61 ]
+
+The endianness flag is used on the CODEC side to specify an
+ambivalence to endian, typically because it is lost over the hardware
+link. This device receives audio over a SoundWire DAI and as such
+should have endianness applied.
+
+Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
+Link: https://lore.kernel.org/r/20220504170905.332415-31-ckeepax@opensource.cirrus.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/rt711.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/sound/soc/codecs/rt711.c b/sound/soc/codecs/rt711.c
+index ea25fd58d43a..9838fb4d5b9c 100644
+--- a/sound/soc/codecs/rt711.c
++++ b/sound/soc/codecs/rt711.c
+@@ -950,6 +950,7 @@ static const struct snd_soc_component_driver soc_codec_dev_rt711 = {
+ .num_dapm_routes = ARRAY_SIZE(rt711_audio_map),
+ .set_jack = rt711_set_jack_detect,
+ .remove = rt711_remove,
++ .endianness = 1,
+ };
+
+ static int rt711_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
+--
+2.35.1
+
--- /dev/null
+From d26c035669a628acc9dc80677459ac0e5c907b80 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 4 May 2022 18:08:58 +0100
+Subject: ASoC: rt711-sdca: Add endianness flag in snd_soc_component_driver
+
+From: Charles Keepax <ckeepax@opensource.cirrus.com>
+
+[ Upstream commit 3e50a5001055d79c04ea1c79fe4b4ff937a3339c ]
+
+The endianness flag is used on the CODEC side to specify an
+ambivalence to endian, typically because it is lost over the hardware
+link. This device receives audio over a SoundWire DAI and as such
+should have endianness applied.
+
+Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
+Link: https://lore.kernel.org/r/20220504170905.332415-32-ckeepax@opensource.cirrus.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/codecs/rt711-sdca.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/sound/soc/codecs/rt711-sdca.c b/sound/soc/codecs/rt711-sdca.c
+index bdb1375f0338..57629c18db38 100644
+--- a/sound/soc/codecs/rt711-sdca.c
++++ b/sound/soc/codecs/rt711-sdca.c
+@@ -1208,6 +1208,7 @@ static const struct snd_soc_component_driver soc_sdca_dev_rt711 = {
+ .num_dapm_routes = ARRAY_SIZE(rt711_sdca_audio_map),
+ .set_jack = rt711_sdca_set_jack_detect,
+ .remove = rt711_sdca_remove,
++ .endianness = 1,
+ };
+
+ static int rt711_sdca_set_sdw_stream(struct snd_soc_dai *dai, void *sdw_stream,
+--
+2.35.1
+
--- /dev/null
+From 03788502ba50ca5986afc207cf0afc4251ee10d0 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 16 Jun 2022 15:19:53 -0500
+Subject: ASoC: SOF: Intel: hda: Fix compressed stream position tracking
+
+From: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
+
+[ Upstream commit ca7ab1dcf58dfce5bc851bf7e50fd94822c24665 ]
+
+Commit 288fad2f71fa ("ASoC: SOF: Intel: hda: add quirks for HDAudio DMA position information")
+modified the PCM path only, but left the compressed data patch using an
+obsolete option.
+Move the functionality in a helper that can be called for both PCM and
+compressed data.
+
+Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+Fixes: 288fad2f71fa ("ASoC: SOF: Intel: hda: add quirks for HDAudio DMA position information")
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
+Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+Link: https://lore.kernel.org/r/20220616201953.130876-1-pierre-louis.bossart@linux.intel.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/sof/intel/hda-pcm.c | 74 +------------------------
+ sound/soc/sof/intel/hda-stream.c | 94 ++++++++++++++++++++++++++++++--
+ sound/soc/sof/intel/hda.h | 3 +
+ 3 files changed, 94 insertions(+), 77 deletions(-)
+
+diff --git a/sound/soc/sof/intel/hda-pcm.c b/sound/soc/sof/intel/hda-pcm.c
+index dc1f743730c0..6888e0a4665d 100644
+--- a/sound/soc/sof/intel/hda-pcm.c
++++ b/sound/soc/sof/intel/hda-pcm.c
+@@ -192,79 +192,7 @@ snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
+ goto found;
+ }
+
+- switch (sof_hda_position_quirk) {
+- case SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY:
+- /*
+- * This legacy code, inherited from the Skylake driver,
+- * mixes DPIB registers and DPIB DDR updates and
+- * does not seem to follow any known hardware recommendations.
+- * It's not clear e.g. why there is a different flow
+- * for capture and playback, the only information that matters is
+- * what traffic class is used, and on all SOF-enabled platforms
+- * only VC0 is supported so the work-around was likely not necessary
+- * and quite possibly wrong.
+- */
+-
+- /* DPIB/posbuf position mode:
+- * For Playback, Use DPIB register from HDA space which
+- * reflects the actual data transferred.
+- * For Capture, Use the position buffer for pointer, as DPIB
+- * is not accurate enough, its update may be completed
+- * earlier than the data written to DDR.
+- */
+- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+- pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+- AZX_REG_VS_SDXDPIB_XBASE +
+- (AZX_REG_VS_SDXDPIB_XINTERVAL *
+- hstream->index));
+- } else {
+- /*
+- * For capture stream, we need more workaround to fix the
+- * position incorrect issue:
+- *
+- * 1. Wait at least 20us before reading position buffer after
+- * the interrupt generated(IOC), to make sure position update
+- * happens on frame boundary i.e. 20.833uSec for 48KHz.
+- * 2. Perform a dummy Read to DPIB register to flush DMA
+- * position value.
+- * 3. Read the DMA Position from posbuf. Now the readback
+- * value should be >= period boundary.
+- */
+- usleep_range(20, 21);
+- snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+- AZX_REG_VS_SDXDPIB_XBASE +
+- (AZX_REG_VS_SDXDPIB_XINTERVAL *
+- hstream->index));
+- pos = snd_hdac_stream_get_pos_posbuf(hstream);
+- }
+- break;
+- case SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS:
+- /*
+- * In case VC1 traffic is disabled this is the recommended option
+- */
+- pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
+- AZX_REG_VS_SDXDPIB_XBASE +
+- (AZX_REG_VS_SDXDPIB_XINTERVAL *
+- hstream->index));
+- break;
+- case SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE:
+- /*
+- * This is the recommended option when VC1 is enabled.
+- * While this isn't needed for SOF platforms it's added for
+- * consistency and debug.
+- */
+- pos = snd_hdac_stream_get_pos_posbuf(hstream);
+- break;
+- default:
+- dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n",
+- sof_hda_position_quirk);
+- pos = 0;
+- break;
+- }
+-
+- if (pos >= hstream->bufsize)
+- pos = 0;
+-
++ pos = hda_dsp_stream_get_position(hstream, substream->stream, true);
+ found:
+ pos = bytes_to_frames(substream->runtime, pos);
+
+diff --git a/sound/soc/sof/intel/hda-stream.c b/sound/soc/sof/intel/hda-stream.c
+index daeb64c495e4..d95ae17e81cc 100644
+--- a/sound/soc/sof/intel/hda-stream.c
++++ b/sound/soc/sof/intel/hda-stream.c
+@@ -707,12 +707,13 @@ bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev)
+ }
+
+ static void
+-hda_dsp_set_bytes_transferred(struct hdac_stream *hstream, u64 buffer_size)
++hda_dsp_compr_bytes_transferred(struct hdac_stream *hstream, int direction)
+ {
++ u64 buffer_size = hstream->bufsize;
+ u64 prev_pos, pos, num_bytes;
+
+ div64_u64_rem(hstream->curr_pos, buffer_size, &prev_pos);
+- pos = snd_hdac_stream_get_pos_posbuf(hstream);
++ pos = hda_dsp_stream_get_position(hstream, direction, false);
+
+ if (pos < prev_pos)
+ num_bytes = (buffer_size - prev_pos) + pos;
+@@ -748,8 +749,7 @@ static bool hda_dsp_stream_check(struct hdac_bus *bus, u32 status)
+ if (s->substream && sof_hda->no_ipc_position) {
+ snd_sof_pcm_period_elapsed(s->substream);
+ } else if (s->cstream) {
+- hda_dsp_set_bytes_transferred(s,
+- s->cstream->runtime->buffer_size);
++ hda_dsp_compr_bytes_transferred(s, s->cstream->direction);
+ snd_compr_fragment_elapsed(s->cstream);
+ }
+ }
+@@ -1009,3 +1009,89 @@ void hda_dsp_stream_free(struct snd_sof_dev *sdev)
+ devm_kfree(sdev->dev, hda_stream);
+ }
+ }
++
++snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
++ int direction, bool can_sleep)
++{
++ struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
++ struct sof_intel_hda_stream *hda_stream = hstream_to_sof_hda_stream(hext_stream);
++ struct snd_sof_dev *sdev = hda_stream->sdev;
++ snd_pcm_uframes_t pos;
++
++ switch (sof_hda_position_quirk) {
++ case SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY:
++ /*
++ * This legacy code, inherited from the Skylake driver,
++ * mixes DPIB registers and DPIB DDR updates and
++ * does not seem to follow any known hardware recommendations.
++ * It's not clear e.g. why there is a different flow
++ * for capture and playback, the only information that matters is
++ * what traffic class is used, and on all SOF-enabled platforms
++ * only VC0 is supported so the work-around was likely not necessary
++ * and quite possibly wrong.
++ */
++
++ /* DPIB/posbuf position mode:
++ * For Playback, Use DPIB register from HDA space which
++ * reflects the actual data transferred.
++ * For Capture, Use the position buffer for pointer, as DPIB
++ * is not accurate enough, its update may be completed
++ * earlier than the data written to DDR.
++ */
++ if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
++ pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
++ AZX_REG_VS_SDXDPIB_XBASE +
++ (AZX_REG_VS_SDXDPIB_XINTERVAL *
++ hstream->index));
++ } else {
++ /*
++ * For capture stream, we need more workaround to fix the
++ * position incorrect issue:
++ *
++ * 1. Wait at least 20us before reading position buffer after
++ * the interrupt generated(IOC), to make sure position update
++ * happens on frame boundary i.e. 20.833uSec for 48KHz.
++ * 2. Perform a dummy Read to DPIB register to flush DMA
++ * position value.
++ * 3. Read the DMA Position from posbuf. Now the readback
++ * value should be >= period boundary.
++ */
++ if (can_sleep)
++ usleep_range(20, 21);
++
++ snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
++ AZX_REG_VS_SDXDPIB_XBASE +
++ (AZX_REG_VS_SDXDPIB_XINTERVAL *
++ hstream->index));
++ pos = snd_hdac_stream_get_pos_posbuf(hstream);
++ }
++ break;
++ case SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS:
++ /*
++ * In case VC1 traffic is disabled this is the recommended option
++ */
++ pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
++ AZX_REG_VS_SDXDPIB_XBASE +
++ (AZX_REG_VS_SDXDPIB_XINTERVAL *
++ hstream->index));
++ break;
++ case SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE:
++ /*
++ * This is the recommended option when VC1 is enabled.
++ * While this isn't needed for SOF platforms it's added for
++ * consistency and debug.
++ */
++ pos = snd_hdac_stream_get_pos_posbuf(hstream);
++ break;
++ default:
++ dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n",
++ sof_hda_position_quirk);
++ pos = 0;
++ break;
++ }
++
++ if (pos >= hstream->bufsize)
++ pos = 0;
++
++ return pos;
++}
+diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
+index 05e5e158614a..196494ba1245 100644
+--- a/sound/soc/sof/intel/hda.h
++++ b/sound/soc/sof/intel/hda.h
+@@ -557,6 +557,9 @@ int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
+ bool hda_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
+ bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev);
+
++snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
++ int direction, bool can_sleep);
++
+ struct hdac_ext_stream *
+ hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags);
+ int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
+--
+2.35.1
+
--- /dev/null
+From 5f8372f975e5c0988f2ae07ba6b1f2fecc6da518 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Fri, 10 Jun 2022 11:47:35 +0300
+Subject: ASoC: SOF: ipc3-topology: Move and correct size checks in
+ sof_ipc3_control_load_bytes()
+
+From: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
+
+[ Upstream commit c2d1aec3f5da2475aa13a487d329823b7d27d499 ]
+
+Move the size checks prior to allocating memory as these checks do not need
+the data to be allocated and in case of an error we would not need to free
+the allocation.
+
+The max size must not be less than the size of
+struct sof_ipc_ctrl_data + struct sof_abi_hdr as the ABI header needs to
+be present under all circumstances.
+The check was incorrectly used or between the two size checks.
+
+Fixes: b5cee8feb1d4 ("ASoC: SOF: topology: Make control parsing IPC agnostic")
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
+Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
+Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
+Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
+Link: https://lore.kernel.org/r/20220610084735.19397-1-peter.ujfalusi@linux.intel.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ sound/soc/sof/ipc3-topology.c | 23 +++++++++++------------
+ 1 file changed, 11 insertions(+), 12 deletions(-)
+
+diff --git a/sound/soc/sof/ipc3-topology.c b/sound/soc/sof/ipc3-topology.c
+index cdff48c4195f..80fb82ece38d 100644
+--- a/sound/soc/sof/ipc3-topology.c
++++ b/sound/soc/sof/ipc3-topology.c
+@@ -1578,24 +1578,23 @@ static int sof_ipc3_control_load_bytes(struct snd_sof_dev *sdev, struct snd_sof_
+ struct sof_ipc_ctrl_data *cdata;
+ int ret;
+
+- scontrol->ipc_control_data = kzalloc(scontrol->max_size, GFP_KERNEL);
+- if (!scontrol->ipc_control_data)
+- return -ENOMEM;
+-
+- if (scontrol->max_size < sizeof(*cdata) ||
+- scontrol->max_size < sizeof(struct sof_abi_hdr)) {
+- ret = -EINVAL;
+- goto err;
++ if (scontrol->max_size < (sizeof(*cdata) + sizeof(struct sof_abi_hdr))) {
++ dev_err(sdev->dev, "%s: insufficient size for a bytes control: %zu.\n",
++ __func__, scontrol->max_size);
++ return -EINVAL;
+ }
+
+- /* init the get/put bytes data */
+ if (scontrol->priv_size > scontrol->max_size - sizeof(*cdata)) {
+- dev_err(sdev->dev, "err: bytes data size %zu exceeds max %zu.\n",
++ dev_err(sdev->dev,
++ "%s: bytes data size %zu exceeds max %zu.\n", __func__,
+ scontrol->priv_size, scontrol->max_size - sizeof(*cdata));
+- ret = -EINVAL;
+- goto err;
++ return -EINVAL;
+ }
+
++ scontrol->ipc_control_data = kzalloc(scontrol->max_size, GFP_KERNEL);
++ if (!scontrol->ipc_control_data)
++ return -ENOMEM;
++
+ scontrol->size = sizeof(struct sof_ipc_ctrl_data) + scontrol->priv_size;
+
+ cdata = scontrol->ipc_control_data;
+--
+2.35.1
+
--- /dev/null
+From a7e615eec183552fa0a4dab98c81c343d668861d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 28 Jun 2022 12:12:16 -0700
+Subject: i2c: cadence: Unregister the clk notifier in error path
+
+From: Satish Nagireddy <satish.nagireddy@getcruise.com>
+
+[ Upstream commit 3501f0c663063513ad604fb1b3f06af637d3396d ]
+
+This patch ensures that the clock notifier is unregistered
+when driver probe is returning error.
+
+Fixes: df8eb5691c48 ("i2c: Add driver for Cadence I2C controller")
+Signed-off-by: Satish Nagireddy <satish.nagireddy@getcruise.com>
+Tested-by: Lars-Peter Clausen <lars@metafoo.de>
+Reviewed-by: Michal Simek <michal.simek@amd.com>
+Signed-off-by: Wolfram Sang <wsa@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/i2c/busses/i2c-cadence.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c
+index b4c1ad19cdae..3d6f8ee355bf 100644
+--- a/drivers/i2c/busses/i2c-cadence.c
++++ b/drivers/i2c/busses/i2c-cadence.c
+@@ -1338,6 +1338,7 @@ static int cdns_i2c_probe(struct platform_device *pdev)
+ return 0;
+
+ err_clk_dis:
++ clk_notifier_unregister(id->clk, &id->clk_rate_change_nb);
+ clk_disable_unprepare(id->clk);
+ pm_runtime_disable(&pdev->dev);
+ pm_runtime_set_suspended(&pdev->dev);
+--
+2.35.1
+
--- /dev/null
+From d424e4fd04e4dd60761b652168a0d492904783c4 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 22 Jun 2022 08:37:43 +0200
+Subject: i2c: piix4: Fix a memory leak in the EFCH MMIO support
+
+From: Jean Delvare <jdelvare@suse.de>
+
+[ Upstream commit 8ad59b397f86a4d8014966fdc0552095a0c4fb2b ]
+
+The recently added support for EFCH MMIO regions introduced a memory
+leak in that code path. The leak is caused by the fact that
+release_resource() merely removes the resource from the tree but does
+not free its memory. We need to call release_mem_region() instead,
+which does free the memory. As a nice side effect, this brings back
+some symmetry between the legacy and MMIO paths.
+
+Signed-off-by: Jean Delvare <jdelvare@suse.de>
+Reported-by: Yi Zhang <yi.zhang@redhat.com>
+Tested-by: Yi Zhang <yi.zhang@redhat.com>
+Reviewed-by: Terry Bowman <terry.bowman@amd.com>
+Tested-by: Terry Bowman <Terry.Bowman@amd.com>
+Fixes: 7c148722d074 ("i2c: piix4: Add EFCH MMIO support to region request and release")
+Signed-off-by: Wolfram Sang <wsa@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/i2c/busses/i2c-piix4.c | 16 +++++++---------
+ 1 file changed, 7 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
+index ac8e7d60672a..39cb1b7bb865 100644
+--- a/drivers/i2c/busses/i2c-piix4.c
++++ b/drivers/i2c/busses/i2c-piix4.c
+@@ -161,7 +161,6 @@ static const char *piix4_aux_port_name_sb800 = " port 1";
+
+ struct sb800_mmio_cfg {
+ void __iomem *addr;
+- struct resource *res;
+ bool use_mmio;
+ };
+
+@@ -179,13 +178,11 @@ static int piix4_sb800_region_request(struct device *dev,
+ struct sb800_mmio_cfg *mmio_cfg)
+ {
+ if (mmio_cfg->use_mmio) {
+- struct resource *res;
+ void __iomem *addr;
+
+- res = request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR,
+- SB800_PIIX4_FCH_PM_SIZE,
+- "sb800_piix4_smb");
+- if (!res) {
++ if (!request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR,
++ SB800_PIIX4_FCH_PM_SIZE,
++ "sb800_piix4_smb")) {
+ dev_err(dev,
+ "SMBus base address memory region 0x%x already in use.\n",
+ SB800_PIIX4_FCH_PM_ADDR);
+@@ -195,12 +192,12 @@ static int piix4_sb800_region_request(struct device *dev,
+ addr = ioremap(SB800_PIIX4_FCH_PM_ADDR,
+ SB800_PIIX4_FCH_PM_SIZE);
+ if (!addr) {
+- release_resource(res);
++ release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
++ SB800_PIIX4_FCH_PM_SIZE);
+ dev_err(dev, "SMBus base address mapping failed.\n");
+ return -ENOMEM;
+ }
+
+- mmio_cfg->res = res;
+ mmio_cfg->addr = addr;
+
+ return 0;
+@@ -222,7 +219,8 @@ static void piix4_sb800_region_release(struct device *dev,
+ {
+ if (mmio_cfg->use_mmio) {
+ iounmap(mmio_cfg->addr);
+- release_resource(mmio_cfg->res);
++ release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
++ SB800_PIIX4_FCH_PM_SIZE);
+ return;
+ }
+
+--
+2.35.1
+
--- /dev/null
+From 575e141396640d7a4db15a43acc5729128648b19 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 31 May 2022 12:54:20 +0200
+Subject: i40e: Fix dropped jumbo frames statistics
+
+From: Lukasz Cieplicki <lukaszx.cieplicki@intel.com>
+
+[ Upstream commit 1adb1563e7b7ec659379a18e607e8bc3522d8a78 ]
+
+Dropped packets caused by too large frames were not included in
+dropped RX packets statistics.
+Issue was caused by not reading the GL_RXERR1 register. That register
+stores count of packet which was have been dropped due to too large
+size.
+
+Fix it by reading GL_RXERR1 register for each interface.
+
+Repro steps:
+Send a packet larger than the set MTU to SUT
+Observe rx statists: ethtool -S <interface> | grep rx | grep -v ": 0"
+
+Fixes: 41a9e55c89be ("i40e: add missing VSI statistics")
+Signed-off-by: Lukasz Cieplicki <lukaszx.cieplicki@intel.com>
+Signed-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>
+Tested-by: Gurucharan <gurucharanx.g@intel.com> (A Contingent worker at Intel)
+Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/intel/i40e/i40e.h | 16 ++++
+ drivers/net/ethernet/intel/i40e/i40e_main.c | 73 +++++++++++++++++++
+ .../net/ethernet/intel/i40e/i40e_register.h | 13 ++++
+ drivers/net/ethernet/intel/i40e/i40e_type.h | 1 +
+ 4 files changed, 103 insertions(+)
+
+diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h
+index 55c6bce5da61..615aff0798d3 100644
+--- a/drivers/net/ethernet/intel/i40e/i40e.h
++++ b/drivers/net/ethernet/intel/i40e/i40e.h
+@@ -37,6 +37,7 @@
+ #include <net/tc_act/tc_mirred.h>
+ #include <net/udp_tunnel.h>
+ #include <net/xdp_sock.h>
++#include <linux/bitfield.h>
+ #include "i40e_type.h"
+ #include "i40e_prototype.h"
+ #include <linux/net/intel/i40e_client.h>
+@@ -1091,6 +1092,21 @@ static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
+ (u32)(val & 0xFFFFFFFFULL));
+ }
+
++/**
++ * i40e_get_pf_count - get PCI PF count.
++ * @hw: pointer to a hw.
++ *
++ * Reports the function number of the highest PCI physical
++ * function plus 1 as it is loaded from the NVM.
++ *
++ * Return: PCI PF count.
++ **/
++static inline u32 i40e_get_pf_count(struct i40e_hw *hw)
++{
++ return FIELD_GET(I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK,
++ rd32(hw, I40E_GLGEN_PCIFCNCNT));
++}
++
+ /* needed by i40e_ethtool.c */
+ int i40e_up(struct i40e_vsi *vsi);
+ void i40e_down(struct i40e_vsi *vsi);
+diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
+index 46bb1169a004..77eb9c726205 100644
+--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
++++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
+@@ -549,6 +549,47 @@ void i40e_pf_reset_stats(struct i40e_pf *pf)
+ pf->hw_csum_rx_error = 0;
+ }
+
++/**
++ * i40e_compute_pci_to_hw_id - compute index form PCI function.
++ * @vsi: ptr to the VSI to read from.
++ * @hw: ptr to the hardware info.
++ **/
++static u32 i40e_compute_pci_to_hw_id(struct i40e_vsi *vsi, struct i40e_hw *hw)
++{
++ int pf_count = i40e_get_pf_count(hw);
++
++ if (vsi->type == I40E_VSI_SRIOV)
++ return (hw->port * BIT(7)) / pf_count + vsi->vf_id;
++
++ return hw->port + BIT(7);
++}
++
++/**
++ * i40e_stat_update64 - read and update a 64 bit stat from the chip.
++ * @hw: ptr to the hardware info.
++ * @hireg: the high 32 bit reg to read.
++ * @loreg: the low 32 bit reg to read.
++ * @offset_loaded: has the initial offset been loaded yet.
++ * @offset: ptr to current offset value.
++ * @stat: ptr to the stat.
++ *
++ * Since the device stats are not reset at PFReset, they will not
++ * be zeroed when the driver starts. We'll save the first values read
++ * and use them as offsets to be subtracted from the raw values in order
++ * to report stats that count from zero.
++ **/
++static void i40e_stat_update64(struct i40e_hw *hw, u32 hireg, u32 loreg,
++ bool offset_loaded, u64 *offset, u64 *stat)
++{
++ u64 new_data;
++
++ new_data = rd64(hw, loreg);
++
++ if (!offset_loaded || new_data < *offset)
++ *offset = new_data;
++ *stat = new_data - *offset;
++}
++
+ /**
+ * i40e_stat_update48 - read and update a 48 bit stat from the chip
+ * @hw: ptr to the hardware info
+@@ -620,6 +661,34 @@ static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat)
+ *stat += new_data;
+ }
+
++/**
++ * i40e_stats_update_rx_discards - update rx_discards.
++ * @vsi: ptr to the VSI to be updated.
++ * @hw: ptr to the hardware info.
++ * @stat_idx: VSI's stat_counter_idx.
++ * @offset_loaded: ptr to the VSI's stat_offsets_loaded.
++ * @stat_offset: ptr to stat_offset to store first read of specific register.
++ * @stat: ptr to VSI's stat to be updated.
++ **/
++static void
++i40e_stats_update_rx_discards(struct i40e_vsi *vsi, struct i40e_hw *hw,
++ int stat_idx, bool offset_loaded,
++ struct i40e_eth_stats *stat_offset,
++ struct i40e_eth_stats *stat)
++{
++ u64 rx_rdpc, rx_rxerr;
++
++ i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), offset_loaded,
++ &stat_offset->rx_discards, &rx_rdpc);
++ i40e_stat_update64(hw,
++ I40E_GL_RXERR1H(i40e_compute_pci_to_hw_id(vsi, hw)),
++ I40E_GL_RXERR1L(i40e_compute_pci_to_hw_id(vsi, hw)),
++ offset_loaded, &stat_offset->rx_discards_other,
++ &rx_rxerr);
++
++ stat->rx_discards = rx_rdpc + rx_rxerr;
++}
++
+ /**
+ * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
+ * @vsi: the VSI to be updated
+@@ -679,6 +748,10 @@ void i40e_update_eth_stats(struct i40e_vsi *vsi)
+ I40E_GLV_BPTCL(stat_idx),
+ vsi->stat_offsets_loaded,
+ &oes->tx_broadcast, &es->tx_broadcast);
++
++ i40e_stats_update_rx_discards(vsi, hw, stat_idx,
++ vsi->stat_offsets_loaded, oes, es);
++
+ vsi->stat_offsets_loaded = true;
+ }
+
+diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h
+index 1908eed4fa5e..7339003aa17c 100644
+--- a/drivers/net/ethernet/intel/i40e/i40e_register.h
++++ b/drivers/net/ethernet/intel/i40e/i40e_register.h
+@@ -211,6 +211,11 @@
+ #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
+ #define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
+ #define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
++#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */
++#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
++#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
++#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16
++#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
+ #define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */
+ #define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0
+ #define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
+@@ -643,6 +648,14 @@
+ #define I40E_VFQF_HKEY1_MAX_INDEX 12
+ #define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */
+ #define I40E_VFQF_HLUT1_MAX_INDEX 15
++#define I40E_GL_RXERR1H(_i) (0x00318004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
++#define I40E_GL_RXERR1H_MAX_INDEX 143
++#define I40E_GL_RXERR1H_RXERR1H_SHIFT 0
++#define I40E_GL_RXERR1H_RXERR1H_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1H_RXERR1H_SHIFT)
++#define I40E_GL_RXERR1L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */
++#define I40E_GL_RXERR1L_MAX_INDEX 143
++#define I40E_GL_RXERR1L_RXERR1L_SHIFT 0
++#define I40E_GL_RXERR1L_RXERR1L_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1L_RXERR1L_SHIFT)
+ #define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
+ #define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
+ #define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */
+diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h
+index 36a4ca1ffb1a..7b3f30beb757 100644
+--- a/drivers/net/ethernet/intel/i40e/i40e_type.h
++++ b/drivers/net/ethernet/intel/i40e/i40e_type.h
+@@ -1172,6 +1172,7 @@ struct i40e_eth_stats {
+ u64 tx_broadcast; /* bptc */
+ u64 tx_discards; /* tdpc */
+ u64 tx_errors; /* tepc */
++ u64 rx_discards_other; /* rxerr1 */
+ };
+
+ /* Statistics collected per VEB per TC */
+--
+2.35.1
+
--- /dev/null
+From ce75a9779926662312364ea773665f6669a0f11e Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 8 Jun 2022 11:10:56 +0200
+Subject: i40e: Fix VF's MAC Address change on VM
+
+From: Norbert Zulinski <norbertx.zulinski@intel.com>
+
+[ Upstream commit fed0d9f13266a22ce1fc9a97521ef9cdc6271a23 ]
+
+Clear VF MAC from parent PF and remove VF filter from VSI when both
+conditions are true:
+-VIRTCHNL_VF_OFFLOAD_USO is not used
+-VM MAC was not set from PF level
+
+It affects older version of IAVF and it allow them to change MAC
+Address on VM, newer IAVF won't change their behaviour.
+
+Previously it wasn't possible to change VF's MAC Address on VM
+because there is flag on IAVF driver that won't allow to
+change MAC Address if this address is given from PF driver.
+
+Fixes: 155f0ac2c96b ("iavf: allow permanent MAC address to change")
+Signed-off-by: Norbert Zulinski <norbertx.zulinski@intel.com>
+Signed-off-by: Jan Sokolowski <jan.sokolowski@intel.com>
+Tested-by: Konrad Jankowski <konrad0.jankowski@intel.com>
+Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
+index 033ea71763e3..86b0f21287dc 100644
+--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
++++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
+@@ -2147,6 +2147,10 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf, u8 *msg)
+ /* VFs only use TC 0 */
+ vfres->vsi_res[0].qset_handle
+ = le16_to_cpu(vsi->info.qs_handle[0]);
++ if (!(vf->driver_caps & VIRTCHNL_VF_OFFLOAD_USO) && !vf->pf_set_mac) {
++ i40e_del_mac_filter(vsi, vf->default_lan_addr.addr);
++ eth_zero_addr(vf->default_lan_addr.addr);
++ }
+ ether_addr_copy(vfres->vsi_res[0].default_mac_addr,
+ vf->default_lan_addr.addr);
+ }
+--
+2.35.1
+
--- /dev/null
+From 65c56af6bcc95373b50345db2601be158054e6ef Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sat, 2 Jul 2022 03:37:12 -0700
+Subject: ibmvnic: Properly dispose of all skbs during a failover.
+
+From: Rick Lindsley <ricklind@us.ibm.com>
+
+[ Upstream commit 1b18f09d31cfa7148df15a7d5c5e0e86f105f7d1 ]
+
+During a reset, there may have been transmits in flight that are no
+longer valid and cannot be fulfilled. Resetting and clearing the
+queues is insufficient; each skb also needs to be explicitly freed
+so that upper levels are not left waiting for confirmation of a
+transmit that will never happen. If this happens frequently enough,
+the apparent backlog will cause TCP to begin "congestion control"
+unnecessarily, culminating in permanently decreased throughput.
+
+Fixes: d7c0ef36bde03 ("ibmvnic: Free and re-allocate scrqs when tx/rx scrqs change")
+Tested-by: Nick Child <nnac123@linux.ibm.com>
+Reviewed-by: Brian King <brking@linux.vnet.ibm.com>
+Signed-off-by: Rick Lindsley <ricklind@us.ibm.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/ibm/ibmvnic.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c
+index 5c5931dba51d..c4221f89ab18 100644
+--- a/drivers/net/ethernet/ibm/ibmvnic.c
++++ b/drivers/net/ethernet/ibm/ibmvnic.c
+@@ -5774,6 +5774,15 @@ static int ibmvnic_reset_init(struct ibmvnic_adapter *adapter, bool reset)
+ release_sub_crqs(adapter, 0);
+ rc = init_sub_crqs(adapter);
+ } else {
++ /* no need to reinitialize completely, but we do
++ * need to clean up transmits that were in flight
++ * when we processed the reset. Failure to do so
++ * will confound the upper layer, usually TCP, by
++ * creating the illusion of transmits that are
++ * awaiting completion.
++ */
++ clean_tx_pools(adapter);
++
+ rc = reset_sub_crq_queues(adapter);
+ }
+ } else {
+--
+2.35.1
+
--- /dev/null
+From 275bda99fef66d9cdb7637c093d69792d49825a3 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Jul 2022 14:32:13 -0700
+Subject: mptcp: Acquire the subflow socket lock before modifying MP_PRIO flags
+
+From: Mat Martineau <mathew.j.martineau@linux.intel.com>
+
+[ Upstream commit a657430260e5437df16004c8c317821d946b5ead ]
+
+When setting up a subflow's flags for sending MP_PRIO MPTCP options, the
+subflow socket lock was not held while reading and modifying several
+struct members that are also read and modified in mptcp_write_options().
+
+Acquire the subflow socket lock earlier and send the MP_PRIO ACK with
+that lock already acquired. Add a new variant of the
+mptcp_subflow_send_ack() helper to use with the subflow lock held.
+
+Fixes: 067065422fcd ("mptcp: add the outgoing MP_PRIO support")
+Acked-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/mptcp/pm_netlink.c | 5 ++++-
+ net/mptcp/protocol.c | 9 +++++++--
+ net/mptcp/protocol.h | 1 +
+ 3 files changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/net/mptcp/pm_netlink.c b/net/mptcp/pm_netlink.c
+index 88077ea02ed3..3384569f73b8 100644
+--- a/net/mptcp/pm_netlink.c
++++ b/net/mptcp/pm_netlink.c
+@@ -721,11 +721,13 @@ static int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
+ mptcp_for_each_subflow(msk, subflow) {
+ struct sock *ssk = mptcp_subflow_tcp_sock(subflow);
+ struct mptcp_addr_info local;
++ bool slow;
+
+ local_address((struct sock_common *)ssk, &local);
+ if (!addresses_equal(&local, addr, addr->port))
+ continue;
+
++ slow = lock_sock_fast(ssk);
+ if (subflow->backup != bkup)
+ msk->last_snd = NULL;
+ subflow->backup = bkup;
+@@ -733,7 +735,8 @@ static int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
+ subflow->request_bkup = bkup;
+
+ pr_debug("send ack for mp_prio");
+- mptcp_subflow_send_ack(ssk);
++ __mptcp_subflow_send_ack(ssk);
++ unlock_sock_fast(ssk, slow);
+
+ return 0;
+ }
+diff --git a/net/mptcp/protocol.c b/net/mptcp/protocol.c
+index 713077eef04a..b0fb1fc0bd4a 100644
+--- a/net/mptcp/protocol.c
++++ b/net/mptcp/protocol.c
+@@ -506,13 +506,18 @@ static bool tcp_can_send_ack(const struct sock *ssk)
+ (TCPF_SYN_SENT | TCPF_SYN_RECV | TCPF_TIME_WAIT | TCPF_CLOSE | TCPF_LISTEN));
+ }
+
++void __mptcp_subflow_send_ack(struct sock *ssk)
++{
++ if (tcp_can_send_ack(ssk))
++ tcp_send_ack(ssk);
++}
++
+ void mptcp_subflow_send_ack(struct sock *ssk)
+ {
+ bool slow;
+
+ slow = lock_sock_fast(ssk);
+- if (tcp_can_send_ack(ssk))
+- tcp_send_ack(ssk);
++ __mptcp_subflow_send_ack(ssk);
+ unlock_sock_fast(ssk, slow);
+ }
+
+diff --git a/net/mptcp/protocol.h b/net/mptcp/protocol.h
+index 2aab5aff6bcd..ad36a05aa67d 100644
+--- a/net/mptcp/protocol.h
++++ b/net/mptcp/protocol.h
+@@ -584,6 +584,7 @@ void __init mptcp_subflow_init(void);
+ void mptcp_subflow_shutdown(struct sock *sk, struct sock *ssk, int how);
+ void mptcp_close_ssk(struct sock *sk, struct sock *ssk,
+ struct mptcp_subflow_context *subflow);
++void __mptcp_subflow_send_ack(struct sock *ssk);
+ void mptcp_subflow_send_ack(struct sock *ssk);
+ void mptcp_subflow_reset(struct sock *ssk);
+ void mptcp_subflow_queue_clean(struct sock *ssk);
+--
+2.35.1
+
--- /dev/null
+From 245a2244df76c6d6ebf117442a994e3dd175d0ab Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Jul 2022 14:32:12 -0700
+Subject: mptcp: Avoid acquiring PM lock for subflow priority changes
+
+From: Mat Martineau <mathew.j.martineau@linux.intel.com>
+
+[ Upstream commit c21b50d5912b68c4414c60ef5b30416c103f9fd8 ]
+
+The in-kernel path manager code for changing subflow flags acquired both
+the msk socket lock and the PM lock when possibly changing the "backup"
+and "fullmesh" flags. mptcp_pm_nl_mp_prio_send_ack() does not access
+anything protected by the PM lock, and it must release and reacquire
+the PM lock.
+
+By pushing the PM lock to where it is needed in mptcp_pm_nl_fullmesh(),
+the lock is only acquired when the fullmesh flag is changed and the
+backup flag code no longer has to release and reacquire the PM lock. The
+change in locking context requires the MIB update to be modified - move
+that to a better location instead.
+
+This change also makes it possible to call
+mptcp_pm_nl_mp_prio_send_ack() for the userspace PM commands without
+manipulating the in-kernel PM lock.
+
+Fixes: 0f9f696a502e ("mptcp: add set_flags command in PM netlink")
+Acked-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/mptcp/options.c | 3 +++
+ net/mptcp/pm_netlink.c | 8 ++------
+ 2 files changed, 5 insertions(+), 6 deletions(-)
+
+diff --git a/net/mptcp/options.c b/net/mptcp/options.c
+index b548cec86c9d..48e34b81fa1c 100644
+--- a/net/mptcp/options.c
++++ b/net/mptcp/options.c
+@@ -1538,6 +1538,9 @@ void mptcp_write_options(__be32 *ptr, const struct tcp_sock *tp,
+ *ptr++ = mptcp_option(MPTCPOPT_MP_PRIO,
+ TCPOLEN_MPTCP_PRIO,
+ opts->backup, TCPOPT_NOP);
++
++ MPTCP_INC_STATS(sock_net((const struct sock *)tp),
++ MPTCP_MIB_MPPRIOTX);
+ }
+
+ mp_capable_done:
+diff --git a/net/mptcp/pm_netlink.c b/net/mptcp/pm_netlink.c
+index e3dcc5501579..88077ea02ed3 100644
+--- a/net/mptcp/pm_netlink.c
++++ b/net/mptcp/pm_netlink.c
+@@ -720,7 +720,6 @@ static int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
+
+ mptcp_for_each_subflow(msk, subflow) {
+ struct sock *ssk = mptcp_subflow_tcp_sock(subflow);
+- struct sock *sk = (struct sock *)msk;
+ struct mptcp_addr_info local;
+
+ local_address((struct sock_common *)ssk, &local);
+@@ -732,12 +731,9 @@ static int mptcp_pm_nl_mp_prio_send_ack(struct mptcp_sock *msk,
+ subflow->backup = bkup;
+ subflow->send_mp_prio = 1;
+ subflow->request_bkup = bkup;
+- __MPTCP_INC_STATS(sock_net(sk), MPTCP_MIB_MPPRIOTX);
+
+- spin_unlock_bh(&msk->pm.lock);
+ pr_debug("send ack for mp_prio");
+ mptcp_subflow_send_ack(ssk);
+- spin_lock_bh(&msk->pm.lock);
+
+ return 0;
+ }
+@@ -1769,8 +1765,10 @@ static void mptcp_pm_nl_fullmesh(struct mptcp_sock *msk,
+
+ list.ids[list.nr++] = addr->id;
+
++ spin_lock_bh(&msk->pm.lock);
+ mptcp_pm_nl_rm_subflow_received(msk, &list);
+ mptcp_pm_create_subflow_or_signal_addr(msk);
++ spin_unlock_bh(&msk->pm.lock);
+ }
+
+ static int mptcp_nl_set_flags(struct net *net,
+@@ -1788,12 +1786,10 @@ static int mptcp_nl_set_flags(struct net *net,
+ goto next;
+
+ lock_sock(sk);
+- spin_lock_bh(&msk->pm.lock);
+ if (changed & MPTCP_PM_ADDR_FLAG_BACKUP)
+ ret = mptcp_pm_nl_mp_prio_send_ack(msk, addr, bkup);
+ if (changed & MPTCP_PM_ADDR_FLAG_FULLMESH)
+ mptcp_pm_nl_fullmesh(msk, addr);
+- spin_unlock_bh(&msk->pm.lock);
+ release_sock(sk);
+
+ next:
+--
+2.35.1
+
--- /dev/null
+From 73e891a421efbc1a2760d0f8d953b312ad700bc5 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Jul 2022 14:32:16 -0700
+Subject: mptcp: fix local endpoint accounting
+
+From: Paolo Abeni <pabeni@redhat.com>
+
+[ Upstream commit 843b5e75efff04db34fcf9856de53c9e415530a2 ]
+
+In mptcp_pm_nl_rm_addr_or_subflow() we always mark as available
+the id corresponding to the just removed address.
+
+The used bitmap actually tracks only the local IDs: we must
+restrict the operation when a (local) subflow is removed.
+
+Fixes: a88c9e496937 ("mptcp: do not block subflows creation on errors")
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Mat Martineau <mathew.j.martineau@linux.intel.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/mptcp/pm_netlink.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/net/mptcp/pm_netlink.c b/net/mptcp/pm_netlink.c
+index 3384569f73b8..78345278e4a7 100644
+--- a/net/mptcp/pm_netlink.c
++++ b/net/mptcp/pm_netlink.c
+@@ -793,7 +793,8 @@ static void mptcp_pm_nl_rm_addr_or_subflow(struct mptcp_sock *msk,
+ removed = true;
+ __MPTCP_INC_STATS(sock_net(sk), rm_type);
+ }
+- __set_bit(rm_list->ids[i], msk->pm.id_avail_bitmap);
++ if (rm_type == MPTCP_MIB_RMSUBFLOW)
++ __set_bit(rm_list->ids[i], msk->pm.id_avail_bitmap);
+ if (!removed)
+ continue;
+
+--
+2.35.1
+
--- /dev/null
+From 980cdd660a72a4e2bfffd369106b36abd608d9b6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 4 Jul 2022 22:44:05 +0200
+Subject: net/mlx5e: Fix matchall police parameters validation
+
+From: Vlad Buslov <vladbu@nvidia.com>
+
+[ Upstream commit 4d1e07d83ccc87f210e5b852b0a5ea812a2f191c ]
+
+Referenced commit prepared the code for upcoming extension that allows mlx5
+to offload police action attached to flower classifier. However, with
+regard to existing matchall classifier offload validation should be
+reversed as FLOW_ACTION_CONTINUE is the only supported notexceed police
+action type. Fix the problem by allowing FLOW_ACTION_CONTINUE for police
+action and extend scan_tc_matchall_fdb_actions() to only allow such actions
+with matchall classifier.
+
+Fixes: d97b4b105ce7 ("flow_offload: reject offload for all drivers with invalid police parameters")
+Signed-off-by: Vlad Buslov <vladbu@nvidia.com>
+Acked-by: Saeed Mahameed <saeedm@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/mellanox/mlx5/core/en_tc.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+index ec2dfecd7f0f..c01651047448 100644
+--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
++++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+@@ -4503,13 +4503,6 @@ static int mlx5e_policer_validate(const struct flow_action *action,
+ return -EOPNOTSUPP;
+ }
+
+- if (act->police.notexceed.act_id != FLOW_ACTION_PIPE &&
+- act->police.notexceed.act_id != FLOW_ACTION_ACCEPT) {
+- NL_SET_ERR_MSG_MOD(extack,
+- "Offload not supported when conform action is not pipe or ok");
+- return -EOPNOTSUPP;
+- }
+-
+ if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&
+ !flow_action_is_last_entry(action, act)) {
+ NL_SET_ERR_MSG_MOD(extack,
+@@ -4560,6 +4553,12 @@ static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
+ flow_action_for_each(i, act, flow_action) {
+ switch (act->id) {
+ case FLOW_ACTION_POLICE:
++ if (act->police.notexceed.act_id != FLOW_ACTION_CONTINUE) {
++ NL_SET_ERR_MSG_MOD(extack,
++ "Offload not supported when conform action is not continue");
++ return -EOPNOTSUPP;
++ }
++
+ err = mlx5e_policer_validate(flow_action, act, extack);
+ if (err)
+ return err;
+--
+2.35.1
+
--- /dev/null
+From 9b2ab6cab21d3246a3c330d84be1ba5844fbec6f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 7 Apr 2022 10:35:22 +0300
+Subject: net/sched: act_api: Add extack to offload_act_setup() callback
+
+From: Ido Schimmel <idosch@nvidia.com>
+
+[ Upstream commit c2ccf84ecb715bb81dc7f51e69d680a95bf055ae ]
+
+The callback is used by various actions to populate the flow action
+structure prior to offload. Pass extack to this callback so that the
+various actions will be able to report accurate error messages to user
+space.
+
+Signed-off-by: Ido Schimmel <idosch@nvidia.com>
+Reviewed-by: Petr Machata <petrm@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/net/act_api.h | 3 ++-
+ include/net/pkt_cls.h | 6 ++++--
+ net/sched/act_api.c | 4 ++--
+ net/sched/act_csum.c | 3 ++-
+ net/sched/act_ct.c | 3 ++-
+ net/sched/act_gact.c | 3 ++-
+ net/sched/act_gate.c | 3 ++-
+ net/sched/act_mirred.c | 3 ++-
+ net/sched/act_mpls.c | 3 ++-
+ net/sched/act_pedit.c | 3 ++-
+ net/sched/act_police.c | 3 ++-
+ net/sched/act_sample.c | 3 ++-
+ net/sched/act_skbedit.c | 3 ++-
+ net/sched/act_tunnel_key.c | 3 ++-
+ net/sched/act_vlan.c | 3 ++-
+ net/sched/cls_api.c | 16 ++++++++++------
+ net/sched/cls_flower.c | 6 ++++--
+ net/sched/cls_matchall.c | 6 ++++--
+ 18 files changed, 50 insertions(+), 27 deletions(-)
+
+diff --git a/include/net/act_api.h b/include/net/act_api.h
+index 3049cb69c025..9cf6870b526e 100644
+--- a/include/net/act_api.h
++++ b/include/net/act_api.h
+@@ -134,7 +134,8 @@ struct tc_action_ops {
+ (*get_psample_group)(const struct tc_action *a,
+ tc_action_priv_destructor *destructor);
+ int (*offload_act_setup)(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind);
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack);
+ };
+
+ struct tc_action_net {
+diff --git a/include/net/pkt_cls.h b/include/net/pkt_cls.h
+index a3b57a93228a..8cf001aed858 100644
+--- a/include/net/pkt_cls.h
++++ b/include/net/pkt_cls.h
+@@ -547,10 +547,12 @@ tcf_match_indev(struct sk_buff *skb, int ifindex)
+ }
+
+ int tc_setup_offload_action(struct flow_action *flow_action,
+- const struct tcf_exts *exts);
++ const struct tcf_exts *exts,
++ struct netlink_ext_ack *extack);
+ void tc_cleanup_offload_action(struct flow_action *flow_action);
+ int tc_setup_action(struct flow_action *flow_action,
+- struct tc_action *actions[]);
++ struct tc_action *actions[],
++ struct netlink_ext_ack *extack);
+
+ int tc_setup_cb_call(struct tcf_block *block, enum tc_setup_type type,
+ void *type_data, bool err_stop, bool rtnl_held);
+diff --git a/net/sched/act_api.c b/net/sched/act_api.c
+index 6fa9e7b1406a..817065aa2833 100644
+--- a/net/sched/act_api.c
++++ b/net/sched/act_api.c
+@@ -195,7 +195,7 @@ static int offload_action_init(struct flow_offload_action *fl_action,
+ if (act->ops->offload_act_setup) {
+ spin_lock_bh(&act->tcfa_lock);
+ err = act->ops->offload_act_setup(act, fl_action, NULL,
+- false);
++ false, extack);
+ spin_unlock_bh(&act->tcfa_lock);
+ return err;
+ }
+@@ -271,7 +271,7 @@ static int tcf_action_offload_add_ex(struct tc_action *action,
+ if (err)
+ goto fl_err;
+
+- err = tc_setup_action(&fl_action->action, actions);
++ err = tc_setup_action(&fl_action->action, actions, extack);
+ if (err) {
+ NL_SET_ERR_MSG_MOD(extack,
+ "Failed to setup tc actions for offload");
+diff --git a/net/sched/act_csum.c b/net/sched/act_csum.c
+index e0f515b774ca..22847ee009ef 100644
+--- a/net/sched/act_csum.c
++++ b/net/sched/act_csum.c
+@@ -696,7 +696,8 @@ static size_t tcf_csum_get_fill_size(const struct tc_action *act)
+ }
+
+ static int tcf_csum_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ if (bind) {
+ struct flow_action_entry *entry = entry_data;
+diff --git a/net/sched/act_ct.c b/net/sched/act_ct.c
+index b3ca837fd4e8..e013253b10d1 100644
+--- a/net/sched/act_ct.c
++++ b/net/sched/act_ct.c
+@@ -1584,7 +1584,8 @@ static void tcf_stats_update(struct tc_action *a, u64 bytes, u64 packets,
+ }
+
+ static int tcf_ct_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ if (bind) {
+ struct flow_action_entry *entry = entry_data;
+diff --git a/net/sched/act_gact.c b/net/sched/act_gact.c
+index bde6a6c01e64..db84a0473cc1 100644
+--- a/net/sched/act_gact.c
++++ b/net/sched/act_gact.c
+@@ -253,7 +253,8 @@ static size_t tcf_gact_get_fill_size(const struct tc_action *act)
+ }
+
+ static int tcf_gact_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ if (bind) {
+ struct flow_action_entry *entry = entry_data;
+diff --git a/net/sched/act_gate.c b/net/sched/act_gate.c
+index d56e73843a4b..fd5155274733 100644
+--- a/net/sched/act_gate.c
++++ b/net/sched/act_gate.c
+@@ -619,7 +619,8 @@ static int tcf_gate_get_entries(struct flow_action_entry *entry,
+ }
+
+ static int tcf_gate_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ int err;
+
+diff --git a/net/sched/act_mirred.c b/net/sched/act_mirred.c
+index 39acd1d18609..70a6a4447e6b 100644
+--- a/net/sched/act_mirred.c
++++ b/net/sched/act_mirred.c
+@@ -460,7 +460,8 @@ static void tcf_offload_mirred_get_dev(struct flow_action_entry *entry,
+ }
+
+ static int tcf_mirred_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ if (bind) {
+ struct flow_action_entry *entry = entry_data;
+diff --git a/net/sched/act_mpls.c b/net/sched/act_mpls.c
+index b9ff3459fdab..23fcfa5605df 100644
+--- a/net/sched/act_mpls.c
++++ b/net/sched/act_mpls.c
+@@ -385,7 +385,8 @@ static int tcf_mpls_search(struct net *net, struct tc_action **a, u32 index)
+ }
+
+ static int tcf_mpls_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ if (bind) {
+ struct flow_action_entry *entry = entry_data;
+diff --git a/net/sched/act_pedit.c b/net/sched/act_pedit.c
+index 211c757bfc3c..8fccc914f464 100644
+--- a/net/sched/act_pedit.c
++++ b/net/sched/act_pedit.c
+@@ -510,7 +510,8 @@ static int tcf_pedit_search(struct net *net, struct tc_action **a, u32 index)
+ }
+
+ static int tcf_pedit_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ if (bind) {
+ struct flow_action_entry *entry = entry_data;
+diff --git a/net/sched/act_police.c b/net/sched/act_police.c
+index f4d917705263..77c17e9b46d1 100644
+--- a/net/sched/act_police.c
++++ b/net/sched/act_police.c
+@@ -442,7 +442,8 @@ static int tcf_police_act_to_flow_act(int tc_act, u32 *extval)
+ }
+
+ static int tcf_police_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ if (bind) {
+ struct flow_action_entry *entry = entry_data;
+diff --git a/net/sched/act_sample.c b/net/sched/act_sample.c
+index 9a22cdda6bbd..2f7f5e44d28c 100644
+--- a/net/sched/act_sample.c
++++ b/net/sched/act_sample.c
+@@ -291,7 +291,8 @@ static void tcf_offload_sample_get_group(struct flow_action_entry *entry,
+ }
+
+ static int tcf_sample_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ if (bind) {
+ struct flow_action_entry *entry = entry_data;
+diff --git a/net/sched/act_skbedit.c b/net/sched/act_skbedit.c
+index ceba11b198bb..8cd8e506c9c9 100644
+--- a/net/sched/act_skbedit.c
++++ b/net/sched/act_skbedit.c
+@@ -328,7 +328,8 @@ static size_t tcf_skbedit_get_fill_size(const struct tc_action *act)
+ }
+
+ static int tcf_skbedit_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ if (bind) {
+ struct flow_action_entry *entry = entry_data;
+diff --git a/net/sched/act_tunnel_key.c b/net/sched/act_tunnel_key.c
+index 23aba03d26a8..3c6f40478c81 100644
+--- a/net/sched/act_tunnel_key.c
++++ b/net/sched/act_tunnel_key.c
+@@ -808,7 +808,8 @@ static int tcf_tunnel_encap_get_tunnel(struct flow_action_entry *entry,
+ static int tcf_tunnel_key_offload_act_setup(struct tc_action *act,
+ void *entry_data,
+ u32 *index_inc,
+- bool bind)
++ bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ int err;
+
+diff --git a/net/sched/act_vlan.c b/net/sched/act_vlan.c
+index 883454c4f921..8c89bce99cbd 100644
+--- a/net/sched/act_vlan.c
++++ b/net/sched/act_vlan.c
+@@ -369,7 +369,8 @@ static size_t tcf_vlan_get_fill_size(const struct tc_action *act)
+ }
+
+ static int tcf_vlan_offload_act_setup(struct tc_action *act, void *entry_data,
+- u32 *index_inc, bool bind)
++ u32 *index_inc, bool bind,
++ struct netlink_ext_ack *extack)
+ {
+ if (bind) {
+ struct flow_action_entry *entry = entry_data;
+diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c
+index f0699f39afdb..2d4dc1468a9a 100644
+--- a/net/sched/cls_api.c
++++ b/net/sched/cls_api.c
+@@ -3513,11 +3513,13 @@ EXPORT_SYMBOL(tc_cleanup_offload_action);
+
+ static int tc_setup_offload_act(struct tc_action *act,
+ struct flow_action_entry *entry,
+- u32 *index_inc)
++ u32 *index_inc,
++ struct netlink_ext_ack *extack)
+ {
+ #ifdef CONFIG_NET_CLS_ACT
+ if (act->ops->offload_act_setup)
+- return act->ops->offload_act_setup(act, entry, index_inc, true);
++ return act->ops->offload_act_setup(act, entry, index_inc, true,
++ extack);
+ else
+ return -EOPNOTSUPP;
+ #else
+@@ -3526,7 +3528,8 @@ static int tc_setup_offload_act(struct tc_action *act,
+ }
+
+ int tc_setup_action(struct flow_action *flow_action,
+- struct tc_action *actions[])
++ struct tc_action *actions[],
++ struct netlink_ext_ack *extack)
+ {
+ int i, j, index, err = 0;
+ struct tc_action *act;
+@@ -3551,7 +3554,7 @@ int tc_setup_action(struct flow_action *flow_action,
+ entry->hw_stats = tc_act_hw_stats(act->hw_stats);
+ entry->hw_index = act->tcfa_index;
+ index = 0;
+- err = tc_setup_offload_act(act, entry, &index);
++ err = tc_setup_offload_act(act, entry, &index, extack);
+ if (!err)
+ j += index;
+ else
+@@ -3570,13 +3573,14 @@ int tc_setup_action(struct flow_action *flow_action,
+ }
+
+ int tc_setup_offload_action(struct flow_action *flow_action,
+- const struct tcf_exts *exts)
++ const struct tcf_exts *exts,
++ struct netlink_ext_ack *extack)
+ {
+ #ifdef CONFIG_NET_CLS_ACT
+ if (!exts)
+ return 0;
+
+- return tc_setup_action(flow_action, exts->actions);
++ return tc_setup_action(flow_action, exts->actions, extack);
+ #else
+ return 0;
+ #endif
+diff --git a/net/sched/cls_flower.c b/net/sched/cls_flower.c
+index ed5e6f08e74a..cddacf49f9e8 100644
+--- a/net/sched/cls_flower.c
++++ b/net/sched/cls_flower.c
+@@ -464,7 +464,8 @@ static int fl_hw_replace_filter(struct tcf_proto *tp,
+ cls_flower.rule->match.key = &f->mkey;
+ cls_flower.classid = f->res.classid;
+
+- err = tc_setup_offload_action(&cls_flower.rule->action, &f->exts);
++ err = tc_setup_offload_action(&cls_flower.rule->action, &f->exts,
++ cls_flower.common.extack);
+ if (err) {
+ kfree(cls_flower.rule);
+ if (skip_sw) {
+@@ -2362,7 +2363,8 @@ static int fl_reoffload(struct tcf_proto *tp, bool add, flow_setup_cb_t *cb,
+ cls_flower.rule->match.mask = &f->mask->key;
+ cls_flower.rule->match.key = &f->mkey;
+
+- err = tc_setup_offload_action(&cls_flower.rule->action, &f->exts);
++ err = tc_setup_offload_action(&cls_flower.rule->action, &f->exts,
++ cls_flower.common.extack);
+ if (err) {
+ kfree(cls_flower.rule);
+ if (tc_skip_sw(f->flags)) {
+diff --git a/net/sched/cls_matchall.c b/net/sched/cls_matchall.c
+index ca5670fd5228..df80c6b185a0 100644
+--- a/net/sched/cls_matchall.c
++++ b/net/sched/cls_matchall.c
+@@ -97,7 +97,8 @@ static int mall_replace_hw_filter(struct tcf_proto *tp,
+ cls_mall.command = TC_CLSMATCHALL_REPLACE;
+ cls_mall.cookie = cookie;
+
+- err = tc_setup_offload_action(&cls_mall.rule->action, &head->exts);
++ err = tc_setup_offload_action(&cls_mall.rule->action, &head->exts,
++ cls_mall.common.extack);
+ if (err) {
+ kfree(cls_mall.rule);
+ mall_destroy_hw_filter(tp, head, cookie, NULL);
+@@ -302,7 +303,8 @@ static int mall_reoffload(struct tcf_proto *tp, bool add, flow_setup_cb_t *cb,
+ TC_CLSMATCHALL_REPLACE : TC_CLSMATCHALL_DESTROY;
+ cls_mall.cookie = (unsigned long)head;
+
+- err = tc_setup_offload_action(&cls_mall.rule->action, &head->exts);
++ err = tc_setup_offload_action(&cls_mall.rule->action, &head->exts,
++ cls_mall.common.extack);
+ if (err) {
+ kfree(cls_mall.rule);
+ if (add && tc_skip_sw(head->flags)) {
+--
+2.35.1
+
--- /dev/null
+From aecb3eabc130d27cce904bbd32f4c812db306b23 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Thu, 7 Apr 2022 10:35:27 +0300
+Subject: net/sched: act_police: Add extack messages for offload failure
+
+From: Ido Schimmel <idosch@nvidia.com>
+
+[ Upstream commit b50e462bc22df4488ec04d85606646e3db5952b8 ]
+
+For better error reporting to user space, add extack messages when
+police action offload fails.
+
+Example:
+
+ # echo 1 > /sys/kernel/tracing/events/netlink/netlink_extack/enable
+
+ # tc filter add dev dummy0 ingress pref 1 proto all matchall skip_sw action police rate 100Mbit burst 10000
+ Error: cls_matchall: Failed to setup flow action.
+ We have an error talking to the kernel
+
+ # cat /sys/kernel/tracing/trace_pipe
+ tc-182 [000] b..1. 21.592969: netlink_extack: msg=act_police: Offload not supported when conform/exceed action is "reclassify"
+ tc-182 [000] ..... 21.592982: netlink_extack: msg=cls_matchall: Failed to setup flow action
+
+ # tc filter add dev dummy0 ingress pref 1 proto all matchall skip_sw action police rate 100Mbit burst 10000 conform-exceed drop/continue
+ Error: cls_matchall: Failed to setup flow action.
+ We have an error talking to the kernel
+
+ # cat /sys/kernel/tracing/trace_pipe
+ tc-184 [000] b..1. 38.882579: netlink_extack: msg=act_police: Offload not supported when conform/exceed action is "continue"
+ tc-184 [000] ..... 38.882593: netlink_extack: msg=cls_matchall: Failed to setup flow action
+
+Signed-off-by: Ido Schimmel <idosch@nvidia.com>
+Reviewed-by: Petr Machata <petrm@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/sched/act_police.c | 17 ++++++++++++++---
+ 1 file changed, 14 insertions(+), 3 deletions(-)
+
+diff --git a/net/sched/act_police.c b/net/sched/act_police.c
+index 77c17e9b46d1..79c8901f66ab 100644
+--- a/net/sched/act_police.c
++++ b/net/sched/act_police.c
+@@ -419,7 +419,8 @@ static int tcf_police_search(struct net *net, struct tc_action **a, u32 index)
+ return tcf_idr_search(tn, a, index);
+ }
+
+-static int tcf_police_act_to_flow_act(int tc_act, u32 *extval)
++static int tcf_police_act_to_flow_act(int tc_act, u32 *extval,
++ struct netlink_ext_ack *extack)
+ {
+ int act_id = -EOPNOTSUPP;
+
+@@ -430,12 +431,20 @@ static int tcf_police_act_to_flow_act(int tc_act, u32 *extval)
+ act_id = FLOW_ACTION_DROP;
+ else if (tc_act == TC_ACT_PIPE)
+ act_id = FLOW_ACTION_PIPE;
++ else if (tc_act == TC_ACT_RECLASSIFY)
++ NL_SET_ERR_MSG_MOD(extack, "Offload not supported when conform/exceed action is \"reclassify\"");
++ else
++ NL_SET_ERR_MSG_MOD(extack, "Unsupported conform/exceed action offload");
+ } else if (TC_ACT_EXT_CMP(tc_act, TC_ACT_GOTO_CHAIN)) {
+ act_id = FLOW_ACTION_GOTO;
+ *extval = tc_act & TC_ACT_EXT_VAL_MASK;
+ } else if (TC_ACT_EXT_CMP(tc_act, TC_ACT_JUMP)) {
+ act_id = FLOW_ACTION_JUMP;
+ *extval = tc_act & TC_ACT_EXT_VAL_MASK;
++ } else if (tc_act == TC_ACT_UNSPEC) {
++ NL_SET_ERR_MSG_MOD(extack, "Offload not supported when conform/exceed action is \"continue\"");
++ } else {
++ NL_SET_ERR_MSG_MOD(extack, "Unsupported conform/exceed action offload");
+ }
+
+ return act_id;
+@@ -467,14 +476,16 @@ static int tcf_police_offload_act_setup(struct tc_action *act, void *entry_data,
+ entry->police.mtu = tcf_police_tcfp_mtu(act);
+
+ act_id = tcf_police_act_to_flow_act(police->tcf_action,
+- &entry->police.exceed.extval);
++ &entry->police.exceed.extval,
++ extack);
+ if (act_id < 0)
+ return act_id;
+
+ entry->police.exceed.act_id = act_id;
+
+ act_id = tcf_police_act_to_flow_act(p->tcfp_result,
+- &entry->police.notexceed.extval);
++ &entry->police.notexceed.extval,
++ extack);
+ if (act_id < 0)
+ return act_id;
+
+--
+2.35.1
+
--- /dev/null
+From 6d882078c1cbc2283812b52f553d16e50178c56d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Mon, 4 Jul 2022 22:44:04 +0200
+Subject: net/sched: act_police: allow 'continue' action offload
+
+From: Vlad Buslov <vladbu@nvidia.com>
+
+[ Upstream commit 052f744f44462cc49b88a125b0f7b93a9e47a9dd ]
+
+Offloading police with action TC_ACT_UNSPEC was erroneously disabled even
+though it was supported by mlx5 matchall offload implementation, which
+didn't verify the action type but instead assumed that any single police
+action attached to matchall classifier is a 'continue' action. Lack of
+action type check made it non-obvious what mlx5 matchall implementation
+actually supports and caused implementers and reviewers of referenced
+commits to disallow it as a part of improved validation code.
+
+Fixes: b8cd5831c61c ("net: flow_offload: add tc police action parameters")
+Fixes: b50e462bc22d ("net/sched: act_police: Add extack messages for offload failure")
+Signed-off-by: Vlad Buslov <vladbu@nvidia.com>
+Reviewed-by: Ido Schimmel <idosch@nvidia.com>
+Tested-by: Ido Schimmel <idosch@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ include/net/flow_offload.h | 1 +
+ net/sched/act_police.c | 2 +-
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h
+index 6484095a8c01..7ac313858037 100644
+--- a/include/net/flow_offload.h
++++ b/include/net/flow_offload.h
+@@ -152,6 +152,7 @@ enum flow_action_id {
+ FLOW_ACTION_PIPE,
+ FLOW_ACTION_VLAN_PUSH_ETH,
+ FLOW_ACTION_VLAN_POP_ETH,
++ FLOW_ACTION_CONTINUE,
+ NUM_FLOW_ACTIONS,
+ };
+
+diff --git a/net/sched/act_police.c b/net/sched/act_police.c
+index 79c8901f66ab..b759628a47c2 100644
+--- a/net/sched/act_police.c
++++ b/net/sched/act_police.c
+@@ -442,7 +442,7 @@ static int tcf_police_act_to_flow_act(int tc_act, u32 *extval,
+ act_id = FLOW_ACTION_JUMP;
+ *extval = tc_act & TC_ACT_EXT_VAL_MASK;
+ } else if (tc_act == TC_ACT_UNSPEC) {
+- NL_SET_ERR_MSG_MOD(extack, "Offload not supported when conform/exceed action is \"continue\"");
++ act_id = FLOW_ACTION_CONTINUE;
+ } else {
+ NL_SET_ERR_MSG_MOD(extack, "Unsupported conform/exceed action offload");
+ }
+--
+2.35.1
+
--- /dev/null
+From 0aec94b5a8473b2b311a5b382b07108861d221a6 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 25 May 2022 21:49:56 -0500
+Subject: pinctrl: sunxi: a83t: Fix NAND function name for some pins
+
+From: Samuel Holland <samuel@sholland.org>
+
+[ Upstream commit aaefa29270d9551b604165a08406543efa9d16f5 ]
+
+The other NAND pins on Port C use the "nand0" function name.
+"nand0" also matches all of the other Allwinner SoCs.
+
+Fixes: 4730f33f0d82 ("pinctrl: sunxi: add allwinner A83T PIO controller support")
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Link: https://lore.kernel.org/r/20220526024956.49500-1-samuel@sholland.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
+index 4ada80317a3b..b5c1a8f363f3 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
+@@ -158,26 +158,26 @@ static const struct sunxi_desc_pin sun8i_a83t_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+- SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */
++ SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+- SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */
++ SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+- SUNXI_FUNCTION(0x2, "nand"), /* DQS */
++ SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+- SUNXI_FUNCTION(0x2, "nand")), /* CE2 */
++ SUNXI_FUNCTION(0x2, "nand0")), /* CE2 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+- SUNXI_FUNCTION(0x2, "nand")), /* CE3 */
++ SUNXI_FUNCTION(0x2, "nand0")), /* CE3 */
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+--
+2.35.1
+
--- /dev/null
+From 7a387990ae9485846d878dc2ab123fac5f4a1575 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 25 May 2022 22:04:25 +0300
+Subject: pinctrl: sunxi: sunxi_pconf_set: use correct offset
+
+From: Andrei Lalaev <andrey.lalaev@gmail.com>
+
+[ Upstream commit cd4c1e65a32afd003b08ad4aafe1e4d3e4e8e61b ]
+
+Some Allwinner SoCs have 2 pinctrls (PIO and R_PIO).
+Previous implementation used absolute pin numbering and it was incorrect
+for R_PIO pinctrl.
+It's necessary to take into account the base pin number.
+
+Fixes: 90be64e27621 ("pinctrl: sunxi: implement pin_config_set")
+Signed-off-by: Andrei Lalaev <andrey.lalaev@gmail.com>
+Reviewed-by: Samuel Holland <samuel@sholland.org>
+Link: https://lore.kernel.org/r/20220525190423.410609-1-andrey.lalaev@gmail.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+index d9327d7d56ee..dd928402af99 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+@@ -544,6 +544,8 @@ static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
+ struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ int i;
+
++ pin -= pctl->desc->pin_base;
++
+ for (i = 0; i < num_configs; i++) {
+ enum pin_config_param param;
+ unsigned long flags;
+--
+2.35.1
+
--- /dev/null
+From ccb8de7f444b30b863a18ba49a912c147f192346 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 5 Jul 2022 21:15:22 +0200
+Subject: r8169: fix accessing unset transport header
+
+From: Heiner Kallweit <hkallweit1@gmail.com>
+
+[ Upstream commit faa4e04e5e140a6d02260289a8fba8fd8d7a3003 ]
+
+66e4c8d95008 ("net: warn if transport header was not set") added
+a check that triggers a warning in r8169, see [0].
+
+The commit referenced in the Fixes tag refers to the change from
+which the patch applies cleanly, there's nothing wrong with this
+commit. It seems the actual issue (not bug, because the warning
+is harmless here) was introduced with bdfa4ed68187
+("r8169: use Giant Send").
+
+[0] https://bugzilla.kernel.org/show_bug.cgi?id=216157
+
+Fixes: 8d520b4de3ed ("r8169: work around RTL8125 UDP hw bug")
+Reported-by: Erhard F. <erhard_f@mailbox.org>
+Tested-by: Erhard F. <erhard_f@mailbox.org>
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Link: https://lore.kernel.org/r/1b2c2b29-3dc0-f7b6-5694-97ec526d51a0@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ drivers/net/ethernet/realtek/r8169_main.c | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c
+index 33f5c5698ccb..642e435c7031 100644
+--- a/drivers/net/ethernet/realtek/r8169_main.c
++++ b/drivers/net/ethernet/realtek/r8169_main.c
+@@ -4190,7 +4190,6 @@ static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
+ static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
+ struct sk_buff *skb, u32 *opts)
+ {
+- u32 transport_offset = (u32)skb_transport_offset(skb);
+ struct skb_shared_info *shinfo = skb_shinfo(skb);
+ u32 mss = shinfo->gso_size;
+
+@@ -4207,7 +4206,7 @@ static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
+ WARN_ON_ONCE(1);
+ }
+
+- opts[0] |= transport_offset << GTTCPHO_SHIFT;
++ opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT;
+ opts[1] |= mss << TD1_MSS_SHIFT;
+ } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ u8 ip_protocol;
+@@ -4235,7 +4234,7 @@ static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
+ else
+ WARN_ON_ONCE(1);
+
+- opts[1] |= transport_offset << TCPHO_SHIFT;
++ opts[1] |= skb_transport_offset(skb) << TCPHO_SHIFT;
+ } else {
+ unsigned int padto = rtl_quirk_packet_padto(tp, skb);
+
+@@ -4402,14 +4401,13 @@ static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
+ struct net_device *dev,
+ netdev_features_t features)
+ {
+- int transport_offset = skb_transport_offset(skb);
+ struct rtl8169_private *tp = netdev_priv(dev);
+
+ if (skb_is_gso(skb)) {
+ if (tp->mac_version == RTL_GIGA_MAC_VER_34)
+ features = rtl8168evl_fix_tso(skb, features);
+
+- if (transport_offset > GTTCPHO_MAX &&
++ if (skb_transport_offset(skb) > GTTCPHO_MAX &&
+ rtl_chip_supports_csum_v2(tp))
+ features &= ~NETIF_F_ALL_TSO;
+ } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
+@@ -4420,7 +4418,7 @@ static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
+ if (rtl_quirk_packet_padto(tp, skb))
+ features &= ~NETIF_F_CSUM_MASK;
+
+- if (transport_offset > TCPHO_MAX &&
++ if (skb_transport_offset(skb) > TCPHO_MAX &&
+ rtl_chip_supports_csum_v2(tp))
+ features &= ~NETIF_F_CSUM_MASK;
+ }
+--
+2.35.1
+
--- /dev/null
+From 54b900d806a204ea86a56e95b3de56f17c08b960 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 3 Jul 2022 10:36:26 +0300
+Subject: selftests: forwarding: fix error message in learning_test
+
+From: Vladimir Oltean <vladimir.oltean@nxp.com>
+
+[ Upstream commit 83844aacab2015da1dba1df0cc61fc4b4c4e8076 ]
+
+When packets are not received, they aren't received on $host1_if, so the
+message talking about the second host not receiving them is incorrect.
+Fix it.
+
+Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning")
+Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Reviewed-by: Ido Schimmel <idosch@nvidia.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/testing/selftests/net/forwarding/lib.sh | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh
+index 412e52e89071..063da0d53462 100644
+--- a/tools/testing/selftests/net/forwarding/lib.sh
++++ b/tools/testing/selftests/net/forwarding/lib.sh
+@@ -1187,7 +1187,7 @@ learning_test()
+ tc -j -s filter show dev $host1_if ingress \
+ | jq -e ".[] | select(.options.handle == 101) \
+ | select(.options.actions[0].stats.packets == 1)" &> /dev/null
+- check_fail $? "Packet reached second host when should not"
++ check_fail $? "Packet reached first host when should not"
+
+ $MZ $host1_if -c 1 -p 64 -a $mac -t ip -q
+ sleep 1
+--
+2.35.1
+
--- /dev/null
+From d7296c464df6e1f28da9afdc3bfdcf81c7dd921d Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 3 Jul 2022 10:36:24 +0300
+Subject: selftests: forwarding: fix flood_unicast_test when h2 supports
+ IFF_UNICAST_FLT
+
+From: Vladimir Oltean <vladimir.oltean@nxp.com>
+
+[ Upstream commit b8e629b05f5d23f9649c901bef09fab8b0c2e4b9 ]
+
+As mentioned in the blamed commit, flood_unicast_test() works by
+checking the match count on a tc filter placed on the receiving
+interface.
+
+But the second host interface (host2_if) has no interest in receiving a
+packet with MAC DA de:ad:be:ef:13:37, so its RX filter drops it even
+before the ingress tc filter gets to be executed. So we will incorrectly
+get the message "Packet was not flooded when should", when in fact, the
+packet was flooded as expected but dropped due to an unrelated reason,
+at some other layer on the receiving side.
+
+Force h2 to accept this packet by temporarily placing it in promiscuous
+mode. Alternatively we could either deliver to its MAC address or use
+tcpdump_start, but this has the fewest complications.
+
+This fixes the "flooding" test from bridge_vlan_aware.sh and
+bridge_vlan_unaware.sh, which calls flood_test from the lib.
+
+Fixes: 236dd50bf67a ("selftests: forwarding: Add a test for flooded traffic")
+Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Reviewed-by: Ido Schimmel <idosch@nvidia.com>
+Tested-by: Ido Schimmel <idosch@nvidia.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/testing/selftests/net/forwarding/lib.sh | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh
+index 664b9ecaf228..823e5cef062d 100644
+--- a/tools/testing/selftests/net/forwarding/lib.sh
++++ b/tools/testing/selftests/net/forwarding/lib.sh
+@@ -1242,6 +1242,7 @@ flood_test_do()
+
+ # Add an ACL on `host2_if` which will tell us whether the packet
+ # was flooded to it or not.
++ ip link set $host2_if promisc on
+ tc qdisc add dev $host2_if ingress
+ tc filter add dev $host2_if ingress protocol ip pref 1 handle 101 \
+ flower dst_mac $mac action drop
+@@ -1259,6 +1260,7 @@ flood_test_do()
+
+ tc filter del dev $host2_if ingress protocol ip pref 1 handle 101 flower
+ tc qdisc del dev $host2_if ingress
++ ip link set $host2_if promisc off
+
+ return $err
+ }
+--
+2.35.1
+
--- /dev/null
+From 79c630b236d282794a6dc4c3418447582c9af900 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Sun, 3 Jul 2022 10:36:25 +0300
+Subject: selftests: forwarding: fix learning_test when h1 supports
+ IFF_UNICAST_FLT
+
+From: Vladimir Oltean <vladimir.oltean@nxp.com>
+
+[ Upstream commit 1a635d3e1c80626237fdae47a5545b6655d8d81c ]
+
+The first host interface has by default no interest in receiving packets
+MAC DA de:ad:be:ef:13:37, so it might drop them before they hit the tc
+filter and this might confuse the selftest.
+
+Enable promiscuous mode such that the filter properly counts received
+packets.
+
+Fixes: d4deb01467ec ("selftests: forwarding: Add a test for FDB learning")
+Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Reviewed-by: Ido Schimmel <idosch@nvidia.com>
+Tested-by: Ido Schimmel <idosch@nvidia.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ tools/testing/selftests/net/forwarding/lib.sh | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/tools/testing/selftests/net/forwarding/lib.sh b/tools/testing/selftests/net/forwarding/lib.sh
+index 823e5cef062d..412e52e89071 100644
+--- a/tools/testing/selftests/net/forwarding/lib.sh
++++ b/tools/testing/selftests/net/forwarding/lib.sh
+@@ -1176,6 +1176,7 @@ learning_test()
+ # FDB entry was installed.
+ bridge link set dev $br_port1 flood off
+
++ ip link set $host1_if promisc on
+ tc qdisc add dev $host1_if ingress
+ tc filter add dev $host1_if ingress protocol ip pref 1 handle 101 \
+ flower dst_mac $mac action drop
+@@ -1225,6 +1226,7 @@ learning_test()
+
+ tc filter del dev $host1_if ingress protocol ip pref 1 handle 101 flower
+ tc qdisc del dev $host1_if ingress
++ ip link set $host1_if promisc off
+
+ bridge link set dev $br_port1 flood on
+
+--
+2.35.1
+
fscache-fix-if-condition-in-fscache_wait_on_volume_collision.patch
powerpc-powernv-delay-rng-platform-device-creation-until-later-in-boot.patch
net-dsa-qca8k-reset-cpu-port-on-mtu-change.patch
+arm-meson-fix-refcount-leak-in-meson_smp_prepare_cpu.patch
+pinctrl-sunxi-a83t-fix-nand-function-name-for-some-p.patch
+srcu-tighten-cleanup_srcu_struct-gp-checks.patch
+asoc-rt711-add-endianness-flag-in-snd_soc_component_.patch
+asoc-rt711-sdca-add-endianness-flag-in-snd_soc_compo.patch
+asoc-codecs-rt700-rt711-rt711-sdca-resume-bus-codec-.patch
+asoc-sof-ipc3-topology-move-and-correct-size-checks-.patch
+asoc-sof-intel-hda-fix-compressed-stream-position-tr.patch
+arm64-dts-qcom-sm8450-fix-interconnects-property-of-.patch
+arm64-dts-qcom-msm8994-fix-cpu6-7-reg-values.patch
+arm64-dts-qcom-sdm845-use-dispcc-ahb-clock-for-mdss-.patch
+arm-mxs_defconfig-enable-the-framebuffer.patch
+arm64-dts-imx8mp-evk-correct-mmc-pad-settings.patch
+arm64-dts-imx8mp-evk-correct-the-uart2-pinctl-value.patch
+arm64-dts-imx8mp-evk-correct-gpio-led-pad-settings.patch
+arm64-dts-imx8mp-evk-correct-vbus-pad-settings.patch
+arm64-dts-imx8mp-evk-correct-eqos-pad-settings.patch
+arm64-dts-imx8mp-evk-correct-i2c5-pad-settings.patch
+arm64-dts-imx8mp-evk-correct-i2c1-pad-settings.patch
+arm64-dts-imx8mp-evk-correct-i2c3-pad-settings.patch
+arm64-dts-imx8mp-phyboard-pollux-rdk-correct-uart-pa.patch
+arm64-dts-imx8mp-phyboard-pollux-rdk-correct-eqos-pa.patch
+arm64-dts-imx8mp-phyboard-pollux-rdk-correct-i2c2-mm.patch
+pinctrl-sunxi-sunxi_pconf_set-use-correct-offset.patch
+arm64-dts-qcom-msm8992-fix-vdd_lvs1_2-supply-typo.patch
+arm-at91-pm-use-proper-compatible-for-sama5d2-s-rtc.patch
+arm-at91-pm-use-proper-compatibles-for-sam9x60-s-rtc.patch
+arm-at91-pm-use-proper-compatibles-for-sama7g5-s-rtc.patch
+arm-dts-at91-sam9x60ek-fix-eeprom-compatible-and-siz.patch
+arm-dts-at91-sama5d2_icp-fix-eeprom-compatibles.patch
+arm-at91-fix-soc-detection-for-sam9x60-sips.patch
+xsk-clear-page-contiguity-bit-when-unmapping-pool.patch
+i2c-piix4-fix-a-memory-leak-in-the-efch-mmio-support.patch
+i40e-fix-dropped-jumbo-frames-statistics.patch
+i40e-fix-vf-s-mac-address-change-on-vm.patch
+arm-dts-stm32-add-missing-usbh-clock-and-fix-clk-ord.patch
+ibmvnic-properly-dispose-of-all-skbs-during-a-failov.patch
+selftests-forwarding-fix-flood_unicast_test-when-h2-.patch
+selftests-forwarding-fix-learning_test-when-h1-suppo.patch
+selftests-forwarding-fix-error-message-in-learning_t.patch
+acpi-cppc-check-_osc-for-flexible-address-space.patch
+acpi-bus-set-cppc-_osc-bits-for-all-and-when-cppc_li.patch
+acpi-cppc-only-probe-for-_cpc-if-cppc-v2-is-acked.patch
+acpi-cppc-don-t-require-_osc-if-x86_feature_cppc-is-.patch
+net-mlx5e-fix-matchall-police-parameters-validation.patch
+mptcp-avoid-acquiring-pm-lock-for-subflow-priority-c.patch
+mptcp-acquire-the-subflow-socket-lock-before-modifyi.patch
+mptcp-fix-local-endpoint-accounting.patch
+r8169-fix-accessing-unset-transport-header.patch
+i2c-cadence-unregister-the-clk-notifier-in-error-pat.patch
+net-sched-act_api-add-extack-to-offload_act_setup-ca.patch
+net-sched-act_police-add-extack-messages-for-offload.patch
+net-sched-act_police-allow-continue-action-offload.patch
--- /dev/null
+From b20db5acba805abb0e7b1ae386cadc20e087a498 Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Wed, 12 Jan 2022 09:52:44 -0800
+Subject: srcu: Tighten cleanup_srcu_struct() GP checks
+
+From: Paul E. McKenney <paulmck@kernel.org>
+
+[ Upstream commit 8ed00760203d8018bee042fbfe8e076579be2c2b ]
+
+Currently, cleanup_srcu_struct() checks for a grace period in progress,
+but it does not check for a grace period that has not yet started but
+which might start at any time. Such a situation could result in a
+use-after-free bug, so this commit adds a check for a grace period that
+is needed but not yet started to cleanup_srcu_struct().
+
+Signed-off-by: Paul E. McKenney <paulmck@kernel.org>
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ kernel/rcu/srcutree.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/kernel/rcu/srcutree.c b/kernel/rcu/srcutree.c
+index 6833d8887181..d30e4db04506 100644
+--- a/kernel/rcu/srcutree.c
++++ b/kernel/rcu/srcutree.c
+@@ -382,9 +382,11 @@ void cleanup_srcu_struct(struct srcu_struct *ssp)
+ return; /* Forgot srcu_barrier(), so just leak it! */
+ }
+ if (WARN_ON(rcu_seq_state(READ_ONCE(ssp->srcu_gp_seq)) != SRCU_STATE_IDLE) ||
++ WARN_ON(rcu_seq_current(&ssp->srcu_gp_seq) != ssp->srcu_gp_seq_needed) ||
+ WARN_ON(srcu_readers_active(ssp))) {
+- pr_info("%s: Active srcu_struct %p state: %d\n",
+- __func__, ssp, rcu_seq_state(READ_ONCE(ssp->srcu_gp_seq)));
++ pr_info("%s: Active srcu_struct %p read state: %d gp state: %lu/%lu\n",
++ __func__, ssp, rcu_seq_state(READ_ONCE(ssp->srcu_gp_seq)),
++ rcu_seq_current(&ssp->srcu_gp_seq), ssp->srcu_gp_seq_needed);
+ return; /* Caller forgot to stop doing call_srcu()? */
+ }
+ free_percpu(ssp->sda);
+--
+2.35.1
+
--- /dev/null
+From af4f133aaa0dc158afe89c5be2e2f149afc1214f Mon Sep 17 00:00:00 2001
+From: Sasha Levin <sashal@kernel.org>
+Date: Tue, 28 Jun 2022 12:18:48 +0300
+Subject: xsk: Clear page contiguity bit when unmapping pool
+
+From: Ivan Malov <ivan.malov@oktetlabs.ru>
+
+[ Upstream commit 512d1999b8e94a5d43fba3afc73e774849674742 ]
+
+When a XSK pool gets mapped, xp_check_dma_contiguity() adds bit 0x1
+to pages' DMA addresses that go in ascending order and at 4K stride.
+
+The problem is that the bit does not get cleared before doing unmap.
+As a result, a lot of warnings from iommu_dma_unmap_page() are seen
+in dmesg, which indicates that lookups by iommu_iova_to_phys() fail.
+
+Fixes: 2b43470add8c ("xsk: Introduce AF_XDP buffer allocation API")
+Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
+Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
+Acked-by: Magnus Karlsson <magnus.karlsson@intel.com>
+Link: https://lore.kernel.org/bpf/20220628091848.534803-1-ivan.malov@oktetlabs.ru
+Signed-off-by: Sasha Levin <sashal@kernel.org>
+---
+ net/xdp/xsk_buff_pool.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/net/xdp/xsk_buff_pool.c b/net/xdp/xsk_buff_pool.c
+index 87bdd71c7bb6..f70112176b7c 100644
+--- a/net/xdp/xsk_buff_pool.c
++++ b/net/xdp/xsk_buff_pool.c
+@@ -332,6 +332,7 @@ static void __xp_dma_unmap(struct xsk_dma_map *dma_map, unsigned long attrs)
+ for (i = 0; i < dma_map->dma_pages_cnt; i++) {
+ dma = &dma_map->dma_pages[i];
+ if (*dma) {
++ *dma &= ~XSK_NEXT_PG_CONTIG_MASK;
+ dma_unmap_page_attrs(dma_map->dev, *dma, PAGE_SIZE,
+ DMA_BIDIRECTIONAL, attrs);
+ *dma = 0;
+--
+2.35.1
+
projects / thirdparty / kernel / stable-queue.git / commitdiff
