clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}

The HW user manual for the Renesas RZ/V2H(P) SoC specifies
that only the WDT1 IP is supposed to be used by Linux,
while the WDT{0,2,3} IPs are supposed to be used by the CM33
and CR8 cores.

Remove the clock and reset entries for WDT{0,2,3} to prevent
interfering with the CM33 and CR8 cores.

This change is harmless as only WDT1 is used by Linux, there
are no users for the WDT{0,2,3} cores.

Fixes: 3aeccbe08171 ("clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT")
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260203124247.7320-4-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index b0e43e5e50dde86460f6e453b1bd7c5d7cfbe242..c3174f40fdb4063c69a132172956f79b840e9b48 100644 (file)
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -280,22 +280,10 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
                                                BUS_MSTOP(11, BIT(15))),
        DEF_MOD("gtm_7_pclk",                   CLK_PLLCLN_DIV16, 4, 10, 2, 10,
                                                BUS_MSTOP(12, BIT(0))),
-       DEF_MOD("wdt_0_clkp",                   CLK_PLLCM33_DIV16, 4, 11, 2, 11,
-                                               BUS_MSTOP(3, BIT(10))),
-       DEF_MOD("wdt_0_clk_loco",               CLK_QEXTAL, 4, 12, 2, 12,
-                                               BUS_MSTOP(3, BIT(10))),
        DEF_MOD("wdt_1_clkp",                   CLK_PLLCLN_DIV16, 4, 13, 2, 13,
                                                BUS_MSTOP(1, BIT(0))),
        DEF_MOD("wdt_1_clk_loco",               CLK_QEXTAL, 4, 14, 2, 14,
                                                BUS_MSTOP(1, BIT(0))),
-       DEF_MOD("wdt_2_clkp",                   CLK_PLLCLN_DIV16, 4, 15, 2, 15,
-                                               BUS_MSTOP(5, BIT(12))),
-       DEF_MOD("wdt_2_clk_loco",               CLK_QEXTAL, 5, 0, 2, 16,
-                                               BUS_MSTOP(5, BIT(12))),
-       DEF_MOD("wdt_3_clkp",                   CLK_PLLCLN_DIV16, 5, 1, 2, 17,
-                                               BUS_MSTOP(5, BIT(13))),
-       DEF_MOD("wdt_3_clk_loco",               CLK_QEXTAL, 5, 2, 2, 18,
-                                               BUS_MSTOP(5, BIT(13))),
        DEF_MOD("rtc_0_clk_rtc",                CLK_PLLCM33_DIV16, 5, 3, 2, 19,
                                                BUS_MSTOP(3, BIT(11) | BIT(12))),
        DEF_MOD("rspi_0_pclk",                  CLK_PLLCLN_DIV8, 5, 4, 2, 20,
@@ -598,10 +586,7 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
        DEF_RST(7, 2, 3, 3),            /* GTM_5_PRESETZ */
        DEF_RST(7, 3, 3, 4),            /* GTM_6_PRESETZ */
        DEF_RST(7, 4, 3, 5),            /* GTM_7_PRESETZ */
-       DEF_RST(7, 5, 3, 6),            /* WDT_0_RESET */
        DEF_RST(7, 6, 3, 7),            /* WDT_1_RESET */
-       DEF_RST(7, 7, 3, 8),            /* WDT_2_RESET */
-       DEF_RST(7, 8, 3, 9),            /* WDT_3_RESET */
        DEF_RST(8, 1, 3, 18),           /* RSCI0_PRESETN */
        DEF_RST(8, 2, 3, 19),           /* RSCI0_TRESETN */
        DEF_RST(8, 3, 3, 20),           /* RSCI1_PRESETN */