PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS milliseconds

[ Upstream commit 22a9120479a40a56c13c5e473a0100fad2e017c0 ]

According to Section 2.2 of the PCI Express Card Electromechanical
Specification (Revision 5.1), in order to ensure that the power and the
reference clock are stable, PERST# has to be deasserted after a delay of
100 milliseconds (TPVPERL).

Currently, it is being assumed that the power is already stable, which
is not necessarily true.

Hence, change the delay to PCIE_T_PVPERL_MS to guarantee that power and
reference clock are stable.

Fixes: f3e25911a430 ("PCI: j721e: Add TI J721E PCIe driver")
Fixes: f96b69713733 ("PCI: j721e: Use T_PERST_CLK_US macro")
Link: https://lore.kernel.org/r/20241104074420.1862932-1-s-vadapalli@ti.com
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index d37e43dbc30b8f5ebcfebb61f5589ae8752d9555..9a0e760e4b523e10f4071cfd1585f85c783642f9 100644 (file)
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -538,15 +538,14 @@ static int j721e_pcie_probe(struct platform_device *pdev)
                pcie->refclk = clk;
 
                /*
-                * The "Power Sequencing and Reset Signal Timings" table of the
-                * PCI Express Card Electromechanical Specification, Revision
-                * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#
-                * should be deasserted after minimum of 100us once REFCLK is
-                * stable. The REFCLK to the connector in RC mode is selected
-                * while enabling the PHY. So deassert PERST# after 100 us.
+                * Section 2.2 of the PCI Express Card Electromechanical
+                * Specification (Revision 5.1) mandates that the deassertion
+                * of the PERST# signal should be delayed by 100 ms (TPVPERL).
+                * This shall ensure that the power and the reference clock
+                * are stable.
                 */
                if (gpiod) {
-                       fsleep(PCIE_T_PERST_CLK_US);
+                       msleep(PCIE_T_PVPERL_MS);
                        gpiod_set_value_cansleep(gpiod, 1);
                }
 
@@ -637,15 +636,14 @@ static int j721e_pcie_resume_noirq(struct device *dev)
                        return ret;
 
                /*
-                * The "Power Sequencing and Reset Signal Timings" table of the
-                * PCI Express Card Electromechanical Specification, Revision
-                * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#
-                * should be deasserted after minimum of 100us once REFCLK is
-                * stable. The REFCLK to the connector in RC mode is selected
-                * while enabling the PHY. So deassert PERST# after 100 us.
+                * Section 2.2 of the PCI Express Card Electromechanical
+                * Specification (Revision 5.1) mandates that the deassertion
+                * of the PERST# signal should be delayed by 100 ms (TPVPERL).
+                * This shall ensure that the power and the reference clock
+                * are stable.
                 */
                if (pcie->reset_gpio) {
-                       fsleep(PCIE_T_PERST_CLK_US);
+                       msleep(PCIE_T_PVPERL_MS);
                        gpiod_set_value_cansleep(pcie->reset_gpio, 1);
                }