clk: mediatek: add dummy clk enable/disable ops for apmixedsys clocks

Starting from commit ac30d90f336 (clk: Ensure the parent clocks are enabled
while reparenting), MediaTek filogic platforms will crash on booting when
initializing mmc devices.

The root cause is that to simplify the code, we reused the topckgen ops for
apmixedsys clocks as they share the get_rate with topckgen clocks while the
clk enable/disable ops are not available for apmixedsys clocks.

Now that a clock will be enabled first before reparenting, we have to add
dummy enable/disable ops for apmixedsys to avoid unexpected behavior when
apmixedsys clocks are the parent clock of the to-be-reparenting clocks.

Fixes: 40746bf429d (clk: mediatek: add clock driver support for MediaTek MT7981 SoC)
Fixes: 37d5a9a29dc (clk: mediatek: add clock driver support for MediaTek MT7986 SoC)
Fixes: ece4e5804f5 (clk: mediatek: add clock driver support for MediaTek MT7987 SoC)
Fixes: 421436981a2 (clk: mediatek: add clock driver support for MediaTek MT7988 SoC)
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 608146523221cb78ae303a8c513f82f16f6d1d83..6130c93d5e65e0db9dbc9faf5e189b6fe1cf9b62 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -566,7 +566,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
        .of_match = mt7981_fixed_pll_compat,
        .probe = mt7981_fixed_pll_probe,
        .priv_auto = sizeof(struct mtk_clk_priv),
-       .ops = &mtk_clk_topckgen_ops,
+       .ops = &mtk_clk_fixed_pll_ops,
        .flags = DM_FLAG_PRE_RELOC,
 };
 

diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index f9d6f9c174907a766ada33670e4c64be0e82c016..cf298af644c1a6353d7be5dbe7537525c5fcbf01 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -573,7 +573,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
        .of_match = mt7986_fixed_pll_compat,
        .probe = mt7986_fixed_pll_probe,
        .priv_auto = sizeof(struct mtk_clk_priv),
-       .ops = &mtk_clk_topckgen_ops,
+       .ops = &mtk_clk_fixed_pll_ops,
        .flags = DM_FLAG_PRE_RELOC,
 };
 

diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c
index 173686a38e87dac7dc788616fa9ec26764ae67d2..b662d680b15908e89f44146177d23c5548193133 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7987.c
+++ b/drivers/clk/mediatek/clk-mt7987.c
@@ -67,7 +67,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
        .of_match = mt7987_fixed_pll_compat,
        .probe = mt7987_fixed_pll_probe,
        .priv_auto = sizeof(struct mtk_clk_priv),
-       .ops = &mtk_clk_topckgen_ops,
+       .ops = &mtk_clk_fixed_pll_ops,
        .flags = DM_FLAG_PRE_RELOC,
 };
 

diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 73fd9c6bea66bbb4d9481d60bd15c169bfadb6ee..c6da42f970bad2eb688b70b0622428215f3c64d5 100644 (file)
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -830,7 +830,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
        .of_match = mt7988_fixed_pll_compat,
        .probe = mt7988_fixed_pll_probe,
        .priv_auto = sizeof(struct mtk_clk_priv),
-       .ops = &mtk_clk_topckgen_ops,
+       .ops = &mtk_clk_fixed_pll_ops,
        .flags = DM_FLAG_PRE_RELOC,
 };
 

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 66683aeb2d72027cd3a2c2d36f7d199a13027411..f91777e968a63477c4e75872af632a6b7c855c51 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -47,6 +47,11 @@ static int mtk_clk_get_id(struct clk *clk)
        return id;
 }
 
+static int mtk_dummy_enable(struct clk *clk)
+{
+       return 0;
+}
+
 static int mtk_gate_enable(void __iomem *base, const struct mtk_gate *gate)
 {
        u32 bit = BIT(gate->shift);
@@ -752,6 +757,12 @@ const struct clk_ops mtk_clk_apmixedsys_ops = {
        .get_rate = mtk_apmixedsys_get_rate,
 };
 
+const struct clk_ops mtk_clk_fixed_pll_ops = {
+       .enable = mtk_dummy_enable,
+       .disable = mtk_dummy_enable,
+       .get_rate = mtk_topckgen_get_rate,
+};
+
 const struct clk_ops mtk_clk_topckgen_ops = {
        .enable = mtk_clk_mux_enable,
        .disable = mtk_clk_mux_disable,

diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c1d9901c10bcdd13ba43a8709d56514d2febf05f..4ef1341aea6a13251b16b9196eb8a0f348fcab11 100644 (file)
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -283,6 +283,7 @@ struct mtk_cg_priv {
 };
 
 extern const struct clk_ops mtk_clk_apmixedsys_ops;
+extern const struct clk_ops mtk_clk_fixed_pll_ops;
 extern const struct clk_ops mtk_clk_topckgen_ops;
 extern const struct clk_ops mtk_clk_infrasys_ops;
 extern const struct clk_ops mtk_clk_gate_ops;