media: verisilicon: AV1: Set IDR flag for intra_only frame type

Intra_only frame could be considered as a key frame so Instantaneous
Decoding Refresh (IDR) flag must be set of the both case and not only
for key frames.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reported-by: Jianfeng Liu <liujianfeng1994@gmail.com>
Fixes: 727a400686a2c ("media: verisilicon: Add Rockchip AV1 decoder")
Cc: stable@vger.kernel.org
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>

diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
index f52b8208e6b93b3d892914be88fbcc9a6e11d8ce..500e94bcb02937c7ff66869ba135f415ba95ef36 100644 (file)
--- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
+++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
@@ -2018,7 +2018,7 @@ static void rockchip_vpu981_av1_dec_set_parameters(struct hantro_ctx *ctx)
                         !!(ctrls->frame->quantization.flags
                            & V4L2_AV1_QUANTIZATION_FLAG_DELTA_Q_PRESENT));
 
-       hantro_reg_write(vpu, &av1_idr_pic_e, !ctrls->frame->frame_type);
+       hantro_reg_write(vpu, &av1_idr_pic_e, IS_INTRA(ctrls->frame->frame_type));
        hantro_reg_write(vpu, &av1_quant_base_qindex, ctrls->frame->quantization.base_q_idx);
        hantro_reg_write(vpu, &av1_bit_depth_y_minus8, ctx->bit_depth - 8);
        hantro_reg_write(vpu, &av1_bit_depth_c_minus8, ctx->bit_depth - 8);