arm64: dts: imx8qxp-mek: add state_100mhz and state_200mhz for usdhc

default, state_100mhz and state_200mhz use the same settings. But current
driver use these to indicate if sd3.0 support.

Add SD gpio pin group (Reset, CD, WP) for usdhc2.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index e092e136854badf71084bf76756aa143c8ad98fa..f1efc0a416da1094cb00ad592aaa73b0ac46f52f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -741,8 +741,10 @@
 &usdhc1 {
        assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
        assigned-clock-rates = <200000000>;
-       pinctrl-names = "default";
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1>;
+       pinctrl-2 = <&pinctrl_usdhc1>;
        bus-width = <8>;
        no-sd;
        no-sdio;
@@ -753,8 +755,10 @@
 &usdhc2 {
        assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
        assigned-clock-rates = <200000000>;
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usdhc2>;
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
        bus-width = <4>;
        vmmc-supply = <&reg_usdhc2_vmmc>;
        cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
@@ -988,6 +992,14 @@
                >;
        };
 
+       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+               fsl,pins = <
+                       IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19                  0x00000021
+                       IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21                       0x00000021
+                       IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22                     0x00000021
+               >;
+       };
+
        pinctrl_usdhc2: usdhc2grp {
                fsl,pins = <
                        IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK                      0x06000041