re PR middle-end/7151 ([sparc] ICE when compiling for UltraSPARC)

2002-09-30  David S. Miller  <davem@redhat.com>

	PR middle-end/7151
	* config/sparc/sparc.md (movdi_insn_sp32_v9): Accept 'e' regs.
	(movdi reg/reg split): Match only on sparc32, and v9 when int regs.

From-SVN: r57722

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e662d8244ae739616fce015a2e9be2009f933a28..56d56f21a4213c49adb4cd7eb35d0801e32c609b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2002-10-01  David S. Miller  <davem@redhat.com>
+
+       PR middle-end/7151
+       * config/sparc/sparc.md (movdi_insn_sp32_v9): Accept 'e' regs.
+       (movdi reg/reg split): Match only on sparc32, and v9 when int regs.
+       
 2002-10-01  David S. Miller  <davem@redhat.com>
            Jan Hubicka <jh@suse.cz>
        

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index ebb6768ef88bd3128a36c743a42a74c12102caec..746dc72c7ea3c9cff1f1e0beca6611782360a0d1 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2517,7 +2517,7 @@
   ;
 }")
 
-;; Be careful, fmovd does not exist when !arch64.
+;; Be careful, fmovd does not exist when !v9.
 ;; We match MEM moves directly when we have correct even
 ;; numbered registers, but fall into splits otherwise.
 ;; The constraint ordering here is really important to
@@ -2531,9 +2531,9 @@
 
 (define_insn "*movdi_insn_sp32_v9"
   [(set (match_operand:DI 0 "nonimmediate_operand"
-                                       "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f")
+                                       "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f,?e,?e,?W")
         (match_operand:DI 1 "input_operand"
-                                       " J,J,U,T,r,o,i,r, f, T, o, f, f"))]
+                                       " J,J,U,T,r,o,i,r, f, T, o, f, f, e, W, e"))]
   "! TARGET_ARCH64 && TARGET_V9
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "@
@@ -2549,9 +2549,13 @@
    ldd\\t%1, %0
    #
    #
-   #"
-  [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
-   (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2")])
+   #
+   fmovd\\t%1, %0
+   ldd\\t%1, %0
+   std\\t%1, %0"
+  [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*,fpmove,fpload,fpstore")
+   (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2,*,*,*")
+   (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")])
 
 (define_insn "*movdi_insn_sp32"
   [(set (match_operand:DI 0 "nonimmediate_operand"
@@ -2861,7 +2865,14 @@
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
         (match_operand:DI 1 "const_double_operand" ""))]
-  "! TARGET_ARCH64 && reload_completed"
+  "reload_completed
+   && (! TARGET_V9
+       || (! TARGET_ARCH64
+           && ((GET_CODE (operands[0]) == REG
+                && REGNO (operands[0]) < 32)
+               || (GET_CODE (operands[0]) == SUBREG
+                   && GET_CODE (SUBREG_REG (operands[0])) == REG
+                   && REGNO (SUBREG_REG (operands[0])) < 32))))"
   [(clobber (const_int 0))]
   "
 {