struct be_error_recovery error_recovery;
};
-/* Used for defered FW config cmds. Add fields to this struct as reqd */
+/* Used for deferred FW config cmds. Add fields to this struct as reqd */
struct be_cmd_work {
struct work_struct work;
struct be_adapter *adapter;
#define be_max_rxqs(adapter) (adapter->res.max_rx_qs)
/* Max number of EQs available for the function (NIC + RoCE (if enabled)) */
#define be_max_func_eqs(adapter) (adapter->res.max_evt_qs)
-/* Max number of EQs available avaialble only for NIC */
+/* Max number of EQs available only for NIC */
#define be_max_nic_eqs(adapter) (adapter->res.max_nic_evt_qs)
#define be_if_cap_flags(adapter) (adapter->res.if_cap_flags)
#define be_max_pf_pool_rss_tables(adapter) \
(adapter->pool_res.max_rss_tables)
-/* Max irqs avaialble for NIC */
+/* Max irqs available for NIC */
#define be_max_irqs(adapter) \
(min_t(u16, be_max_nic_eqs(adapter), num_online_cpus()))
/* Max irqs *needed* for RX queues */
static inline u16 be_max_rx_irqs(struct be_adapter *adapter)
{
- /* If no RSS, need atleast one irq for def-RXQ */
+ /* If no RSS, need at least one irq for def-RXQ */
u16 num = max_t(u16, be_max_rss(adapter), 1);
return min_t(u16, num, be_max_irqs(adapter));
return 0;
}
-/* Uses sycnhronous mcc */
+/* Uses synchronous mcc */
int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
u32 num, u32 domain)
{
return __be_cmd_rx_filter(adapter, flags, value);
}
-/* Uses synchrounous mcc */
+/* Uses synchronous mcc */
int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
{
struct be_mcc_wrb *wrb;
return status;
}
-/* Uses sycn mcc */
+/* Uses sync mcc */
int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
{
struct be_mcc_wrb *wrb;
u8 fw_on_flash_version_string[FW_VER_LEN];
} __packed;
-/******************** Set Flow Contrl *******************/
+/******************** Set Flow Control *******************/
struct be_cmd_req_set_flow_control {
struct be_cmd_req_hdr hdr;
u16 tx_flow_control;
u16 rx_flow_control;
} __packed;
-/******************** Get Flow Contrl *******************/
+/******************** Get Flow Control *******************/
struct be_cmd_req_get_flow_control {
struct be_cmd_req_hdr hdr;
u32 rsvd;
struct be_hw_stats_v2 hw_stats;
};
-/************** get fat capabilites *******************/
+/************** get fat capabilities *******************/
#define MAX_MODULES 27
#define MAX_MODES 4
#define MODE_UART 0
* to HW.
*/
{DRVSTAT_RX_INFO(rx_post_fail)},
- /* Recevied packets dropped due to skb allocation failure */
+ /* Received packets dropped due to skb allocation failure */
{DRVSTAT_RX_INFO(rx_drops_no_skbs)},
/* Received packets dropped due to lack of available fetched buffers
* posted by the driver.
{DRVSTAT_TX_INFO(tx_bytes)},
{DRVSTAT_TX_INFO(tx_pkts)},
{DRVSTAT_TX_INFO(tx_vxlan_offload_pkts)},
- /* Number of skbs queued for trasmission by the driver */
+ /* Number of skbs queued for transmission by the driver */
{DRVSTAT_TX_INFO(tx_reqs)},
/* Number of times the TX queue was stopped due to lack
* of spaces in the TXQ.
ch->tx_count = adapter->num_tx_qs - ch->combined_count;
ch->max_combined = be_max_qp_irqs(adapter);
- /* The user must create atleast one combined channel */
+ /* The user must create at least one combined channel */
ch->max_rx = be_max_rx_irqs(adapter) - 1;
ch->max_tx = be_max_tx_irqs(adapter) - 1;
}
* The software must write this register twice to post any command. First,
* it writes the register with hi=1 and the upper bits of the physical address
* for the MAILBOX structure. Software must poll the ready bit until this
- * is acknowledged. Then, sotware writes the register with hi=0 with the lower
+ * is acknowledged. Then, software writes the register with hi=0 with the lower
* bits in the address. It must poll the ready bit until the command is
* complete. Upon completion, the MAILBOX will contain a valid completion
* queue entry.
#define MPU_EP_CONTROL 0
-/********** MPU semphore: used for SH & BE *************/
+/********** MPU semaphore: used for SH & BE *************/
#define SLIPORT_SOFTRESET_OFFSET 0x5c /* CSR BAR offset */
#define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */
#define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
/* Soft Reset register masks */
#define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */
-/* MPU semphore POST stage values */
+/* MPU semaphore POST stage values */
#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
#define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
};
MODULE_DEVICE_TABLE(pci, be_dev_ids);
-/* Workqueue used by all functions for defering cmd calls to the adapter */
+/* Workqueue used by all functions for deferring cmd calls to the adapter */
static struct workqueue_struct *be_wq;
/* UE Status Low CSR */
struct iphdr *ip;
/* For padded packets, BE HW modifies tot_len field in IP header
- * incorrecly when VLAN tag is inserted by HW.
+ * incorrectly when VLAN tag is inserted by HW.
* For padded packets, Lancer computes incorrect checksum.
*/
eth_hdr_len = ntohs(skb->protocol) == ETH_P_8021Q ?
rxcp->vlanf = 0;
}
- /* As the compl has been parsed, reset it; we wont touch it again */
+ /* As the compl has been parsed, reset it; we won't touch it again */
compl->dw[offsetof(struct amap_eth_rx_compl_v1, valid) / 32] = 0;
queue_tail_inc(&rxo->cq);
if (txcp->status) {
if (lancer_chip(adapter)) {
lancer_update_tx_err(txo, txcp->status);
- /* Reset the adapter incase of TSO,
+ /* Reset the adapter in case of TSO,
* SGE or Parity error
*/
if (txcp->status == LANCER_TX_COMP_LSO_ERR ||
adapter->num_rss_qs =
min(adapter->num_evt_qs, adapter->cfg_num_rx_irqs);
- /* We'll use RSS only if atleast 2 RSS rings are supported. */
+ /* We'll use RSS only if at least 2 RSS rings are supported. */
if (adapter->num_rss_qs < 2)
adapter->num_rss_qs = 0;
/* IRQ is not expected when NAPI is scheduled as the EQ
* will not be armed.
* But, this can happen on Lancer INTx where it takes
- * a while to de-assert INTx or in BE2 where occasionaly
+ * a while to de-assert INTx or in BE2 where occasionally
* an interrupt may be raised even when EQ is unarmed.
* If NAPI is already scheduled, then counting & notifying
* events will orphan them.
/* HW supports only MAX_PORT_RSS_TABLES RSS Policy Tables per port.
* However, this HW limitation is not exposed to the host via any SLI cmd.
* As a result, in the case of SRIOV and in particular multi-partition configs
- * the driver needs to calcuate a proportional share of RSS Tables per PF-pool
+ * the driver needs to calculate a proportional share of RSS Tables per PF-pool
* for distribution between the VFs. This self-imposed limit will determine the
* no: of VFs for which RSS can be enabled.
*/
if (status)
return status;
- /* If a deafault RXQ must be created, we'll use up one RSSQ*/
+ /* If a default RXQ must be created, we'll use up one RSSQ*/
if (res.max_rss_qs && res.max_rss_qs == res.max_rx_qs &&
!(res.if_cap_flags & BE_IF_FLAGS_DEFQ_RSS))
res.max_rss_qs -= 1;
projects / thirdparty / kernel / linux.git / commitdiff
