clk: sunxi: Add support for the A523 CCU

Add a clock driver for the main clock controller on the Allwinner A523
family of SoCs.
As usual, this just describes the clock gates and reset lines for the
few device that U-Boot cares about: USB, Ethernet, MMC, I2C, SPI.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index f44db76c18236871d35eceb8deac3b01f0a3d4b4..74e89b863013aebc6eba5f4ecc6493291ed60a9d 100644 (file)
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -129,4 +129,11 @@ config CLK_SUN50I_A100
          This enables common clock driver support for platforms based
          on Allwinner A100/A133 SoCs.
 
+config CLK_SUN55I_A523
+       bool "Clock driver for Allwinner A523/T527"
+       default MACH_SUN55I_A523
+       help
+         This enables common clock driver support for platforms based
+         on Allwinner A523/T527 SoC.
+
 endif # CLK_SUNXI

diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 7ff71c756e0ab757a89fc9720b07d4f02c8f7136..dd33eabe2edba4d9fa1a3c782a11990f24c8fcfb 100644 (file)
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
 obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
 obj-$(CONFIG_CLK_SUN50I_A100) += clk_a100.o
+obj-$(CONFIG_CLK_SUN55I_A523) += clk_a523.o

diff --git a/drivers/clk/sunxi/clk_a523.c b/drivers/clk/sunxi/clk_a523.c
new file mode 100644 (file)
index 0000000..1de95fb
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a523.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2024 Arm Ltd.
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <clk/sunxi.h>
+#include <linux/bitops.h>
+
+#include <dt-bindings/clock/sun55i-a523-ccu.h>
+#include <dt-bindings/reset/sun55i-a523-ccu.h>
+
+static struct ccu_clk_gate a523_gates[] = {
+       [CLK_PLL_PERIPH0_200M]  = GATE_DUMMY,
+       [CLK_APB1]              = GATE_DUMMY,
+
+       [CLK_BUS_MMC0]          = GATE(0x84c, BIT(0)),
+       [CLK_BUS_MMC1]          = GATE(0x84c, BIT(1)),
+       [CLK_BUS_MMC2]          = GATE(0x84c, BIT(2)),
+       [CLK_BUS_UART0]         = GATE(0x90c, BIT(0)),
+       [CLK_BUS_UART1]         = GATE(0x90c, BIT(1)),
+       [CLK_BUS_UART2]         = GATE(0x90c, BIT(2)),
+       [CLK_BUS_UART3]         = GATE(0x90c, BIT(3)),
+       [CLK_BUS_UART4]         = GATE(0x90c, BIT(4)),
+       [CLK_BUS_UART5]         = GATE(0x90c, BIT(5)),
+       [CLK_BUS_I2C0]          = GATE(0x91c, BIT(0)),
+       [CLK_BUS_I2C1]          = GATE(0x91c, BIT(1)),
+       [CLK_BUS_I2C2]          = GATE(0x91c, BIT(2)),
+       [CLK_BUS_I2C3]          = GATE(0x91c, BIT(3)),
+       [CLK_SPI0]              = GATE(0x940, BIT(31)),
+       [CLK_SPI1]              = GATE(0x944, BIT(31)),
+       [CLK_BUS_SPI0]          = GATE(0x96c, BIT(0)),
+       [CLK_BUS_SPI1]          = GATE(0x96c, BIT(1)),
+
+       [CLK_EMAC0_25M]         = GATE(0x970, BIT(30) | BIT(31)),
+       [CLK_EMAC1_25M]         = GATE(0x974, BIT(30) | BIT(31)),
+       [CLK_BUS_EMAC0]         = GATE(0x97c, BIT(0)),
+       [CLK_BUS_EMAC1]         = GATE(0x98c, BIT(0)),
+
+       [CLK_USB_OHCI0]         = GATE(0xa70, BIT(31)),
+       [CLK_USB_OHCI1]         = GATE(0xa74, BIT(31)),
+       [CLK_BUS_OHCI0]         = GATE(0xa8c, BIT(0)),
+       [CLK_BUS_OHCI1]         = GATE(0xa8c, BIT(1)),
+       [CLK_BUS_EHCI0]         = GATE(0xa8c, BIT(4)),
+       [CLK_BUS_EHCI1]         = GATE(0xa8c, BIT(5)),
+       [CLK_BUS_OTG]           = GATE(0xa8c, BIT(8)),
+};
+
+static struct ccu_reset a523_resets[] = {
+       [RST_BUS_MMC0]          = RESET(0x84c, BIT(16)),
+       [RST_BUS_MMC1]          = RESET(0x84c, BIT(17)),
+       [RST_BUS_MMC2]          = RESET(0x84c, BIT(18)),
+       [RST_BUS_UART0]         = RESET(0x90c, BIT(16)),
+       [RST_BUS_UART1]         = RESET(0x90c, BIT(17)),
+       [RST_BUS_UART2]         = RESET(0x90c, BIT(18)),
+       [RST_BUS_UART3]         = RESET(0x90c, BIT(19)),
+       [RST_BUS_UART4]         = RESET(0x90c, BIT(20)),
+       [RST_BUS_UART5]         = RESET(0x90c, BIT(21)),
+       [RST_BUS_I2C0]          = RESET(0x91c, BIT(16)),
+       [RST_BUS_I2C1]          = RESET(0x91c, BIT(17)),
+       [RST_BUS_I2C2]          = RESET(0x91c, BIT(18)),
+       [RST_BUS_I2C3]          = RESET(0x91c, BIT(19)),
+       [RST_BUS_SPI0]          = RESET(0x96c, BIT(16)),
+       [RST_BUS_SPI1]          = RESET(0x96c, BIT(17)),
+
+       [RST_BUS_EMAC0]         = RESET(0x97c, BIT(16)),
+       [RST_BUS_EMAC1]         = RESET(0x98c, BIT(16) | BIT(17)),
+
+       [RST_USB_PHY0]          = RESET(0xa70, BIT(30)),
+       [RST_USB_PHY1]          = RESET(0xa74, BIT(30)),
+       [RST_BUS_OHCI0]         = RESET(0xa8c, BIT(16)),
+       [RST_BUS_OHCI1]         = RESET(0xa8c, BIT(17)),
+       [RST_BUS_EHCI0]         = RESET(0xa8c, BIT(20)),
+       [RST_BUS_EHCI1]         = RESET(0xa8c, BIT(21)),
+       [RST_BUS_OTG]           = RESET(0xa8c, BIT(24)),
+};
+
+const struct ccu_desc a523_ccu_desc = {
+       .gates  = a523_gates,
+       .resets = a523_resets,
+       .num_gates = ARRAY_SIZE(a523_gates),
+       .num_resets = ARRAY_SIZE(a523_resets),
+};

diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index e0765cbc6dcd9628965c031a26e7e50bc7833eb0..30baabaafcd092aa9f4d1d4fcd59da5f21b0cf43 100644 (file)
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -126,6 +126,7 @@ extern const struct ccu_desc a100_ccu_desc;
 extern const struct ccu_desc h6_r_ccu_desc;
 extern const struct ccu_desc r40_ccu_desc;
 extern const struct ccu_desc v3s_ccu_desc;
+extern const struct ccu_desc a523_ccu_desc;
 
 static const struct udevice_id sunxi_clk_ids[] = {
 #ifdef CONFIG_CLK_SUN4I_A10
@@ -223,6 +224,10 @@ static const struct udevice_id sunxi_clk_ids[] = {
 #ifdef CONFIG_CLK_SUNIV_F1C100S
        { .compatible = "allwinner,suniv-f1c100s-ccu",
          .data = (ulong)&f1c100s_ccu_desc },
+#endif
+#ifdef CONFIG_CLK_SUN55I_A523
+       { .compatible = "allwinner,sun55i-a523-ccu",
+         .data = (ulong)&a523_ccu_desc },
 #endif
        { }
 };