drm/i915/dmc: Add pipe dmc registers and bits for DC Balance

Add pipe dmc registers and  access bits for DC Balance params
configuration and enablement.

--v2:
- Separate register definitions for transcoder and
pipe dmc. (Ankit)
- Use MMIO pipe macros instead of transcoder ones. (Ankit)
- Remove dev_priv use. (Jani, Nikula)

--v3:
- Add all register address, from capital alphabet to small. (Ankit)
- Add EVT CTL registers.
- Add co-author tag.
- Add event flag for Triggering DC Balance.

--v4:
- Add DCB Flip count and balance reset registers.

--v5:
- Correct macro usage for flip count. (Ankit)
- Use register offset in lower case.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-3-mitulkumar.ajitkumar.golani@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index c5aa49921cb9ff1a642bb141481c91ba5e648c58..38e342b45af06b2956406c835ecc92d9f13018ae 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -584,4 +584,64 @@ enum pipedmc_event_id {
 #define PTL_PIPEDMC_EXEC_TIME_LINES(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6b8)
 #define PTL_PIPEDMC_END_OF_EXEC_GB(start_mmioaddr) _MMIO((start_mmioaddr) + 0x6c0)
 
+#define _PIPEDMC_DCB_CTL_A                     0x5f1a0
+#define _PIPEDMC_DCB_CTL_B                     0x5f5a0
+#define PIPEDMC_DCB_CTL(pipe)                  _MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A,\
+                                                          _PIPEDMC_DCB_CTL_B)
+#define  PIPEDMC_ADAPTIVE_DCB_ENABLE           REG_BIT(31)
+
+#define _PIPEDMC_DCB_VBLANK_A                  0x5f1bc
+#define _PIPEDMC_DCB_VBLANK_B                  0x5f5bc
+#define PIPEDMC_DCB_VBLANK(pipe)               _MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A,\
+                                                          _PIPEDMC_DCB_VBLANK_B)
+
+#define _PIPEDMC_DCB_SLOPE_A                   0x5f1b8
+#define _PIPEDMC_DCB_SLOPE_B                   0x5f5b8
+#define PIPEDMC_DCB_SLOPE(pipe)                        _MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A,\
+                                                          _PIPEDMC_DCB_SLOPE_B)
+
+#define _PIPEDMC_DCB_GUARDBAND_A               0x5f1b4
+#define _PIPEDMC_DCB_GUARDBAND_B               0x5f5b4
+#define PIPEDMC_DCB_GUARDBAND(pipe)            _MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A,\
+                                                          _PIPEDMC_DCB_GUARDBAND_B)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A            0x5f1ac
+#define _PIPEDMC_DCB_MAX_INCREASE_B            0x5f5ac
+#define PIPEDMC_DCB_MAX_INCREASE(pipe)         _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A,\
+                                                          _PIPEDMC_DCB_MAX_INCREASE_B)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A            0x5f1b0
+#define _PIPEDMC_DCB_MAX_DECREASE_B            0x5f5b0
+#define PIPEDMC_DCB_MAX_DECREASE(pipe)         _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A,\
+                                                          _PIPEDMC_DCB_MAX_DECREASE_B)
+
+#define _PIPEDMC_DCB_VMIN_A                    0x5f1a4
+#define _PIPEDMC_DCB_VMIN_B                    0x5f5a4
+#define PIPEDMC_DCB_VMIN(pipe)                 _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A,\
+                                                          _PIPEDMC_DCB_VMIN_B)
+
+#define _PIPEDMC_DCB_VMAX_A                    0x5f1a8
+#define _PIPEDMC_DCB_VMAX_B                    0x5f5a8
+#define PIPEDMC_DCB_VMAX(pipe)                 _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A,\
+                                                          _PIPEDMC_DCB_VMAX_B)
+
+#define _PIPEDMC_DCB_DEBUG_A                   0x5f1c0
+#define _PIPEDMC_DCB_DEBUG_B                   0x5f5c0
+#define PIPEDMC_DCB_DEBUG(pipe)                        _MMIO_PIPE(pipe, _PIPEDMC_DCB_DEBUG_A,\
+                                                          _PIPEDMC_DCB_DEBUG_B)
+
+#define _PIPEDMC_EVT_CTL_3_A                   0x5f040
+#define _PIPEDMC_EVT_CTL_3_B                   0x5f440
+#define PIPEDMC_EVT_CTL_3(pipe)                        _MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_3_A,\
+                                                          _PIPEDMC_EVT_CTL_3_B)
+
+#define _PIPEDMC_DCB_FLIP_COUNT_A              0x906a4
+#define _PIPEDMC_DCB_FLIP_COUNT_B              0x986a4
+#define PIPEDMC_DCB_FLIP_COUNT(pipe)           _MMIO_PIPE(pipe, _PIPEDMC_DCB_FLIP_COUNT_A,\
+                                                          _PIPEDMC_DCB_FLIP_COUNT_B)
+
+#define _PIPEDMC_DCB_BALANCE_RESET_A           0x906a8
+#define _PIPEDMC_DCB_BALANCE_RESET_B           0x986a8
+#define PIPEDMC_DCB_BALANCE_RESET(pipe)                _MMIO_PIPE(pipe, _PIPEDMC_DCB_BALANCE_RESET_A,\
+                                                          _PIPEDMC_DCB_BALANCE_RESET_B)
 #endif /* __INTEL_DMC_REGS_H__ */