/* Acknowledge interrupts, if applicable */
if ( netdev_irq_enabled ( netdev ) ) {
- writel ( ( INTELXL_PFINT_DYN_CTL0_CLEARPBA |
- INTELXL_PFINT_DYN_CTL0_INTENA_MASK ),
- intelxl->regs + INTELXL_PFINT_DYN_CTL0 );
+ writel ( ( INTELXL_INT_DYN_CTL_CLEARPBA |
+ INTELXL_INT_DYN_CTL_INTENA_MASK ),
+ ( intelxl->regs + intelxl->intr ) );
}
/* Poll for completed packets */
static void intelxl_irq ( struct net_device *netdev, int enable ) {
struct intelxl_nic *intelxl = netdev->priv;
- if ( enable ) {
- writel ( INTELXL_PFINT_DYN_CTL0_INTENA,
- intelxl->regs + INTELXL_PFINT_DYN_CTL0 );
- } else {
- writel ( 0, intelxl->regs + INTELXL_PFINT_DYN_CTL0 );
- }
+ writel ( ( enable ? INTELXL_INT_DYN_CTL_INTENA : 0 ),
+ ( intelxl->regs + intelxl->intr ) );
}
/** Network device operations */
netdev->dev = &pci->dev;
memset ( intelxl, 0, sizeof ( *intelxl ) );
intelxl->pf = PCI_FUNC ( pci->busdevfn );
+ intelxl->intr = INTELXL_PFINT_DYN_CTL0;
intelxl_init_admin ( &intelxl->command, INTELXL_ADMIN_CMD,
&intelxl_admin_offsets );
intelxl_init_admin ( &intelxl->event, INTELXL_ADMIN_EVT,
/** PF Interrupt Zero Dynamic Control Register */
#define INTELXL_PFINT_DYN_CTL0 0x038480
-#define INTELXL_PFINT_DYN_CTL0_INTENA 0x00000001UL /**< Enable */
-#define INTELXL_PFINT_DYN_CTL0_CLEARPBA 0x00000002UL /**< Acknowledge */
-#define INTELXL_PFINT_DYN_CTL0_INTENA_MASK 0x80000000UL /**< Ignore enable */
+#define INTELXL_INT_DYN_CTL_INTENA 0x00000001UL /**< Enable */
+#define INTELXL_INT_DYN_CTL_CLEARPBA 0x00000002UL /**< Acknowledge */
+#define INTELXL_INT_DYN_CTL_INTENA_MASK 0x80000000UL /**< Ignore enable */
/** PF Interrupt Zero Linked List Register */
#define INTELXL_PFINT_LNKLST0 0x038500
unsigned int vsi;
/** Queue set handle */
unsigned int qset;
+ /** Interrupt control register */
+ unsigned int intr;
/** Admin command queue */
struct intelxl_admin command;