]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: renesas: r9a09g047: Add fcpvd{0,1} nodes
authorTommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Wed, 8 Apr 2026 10:37:03 +0000 (12:37 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Sun, 31 May 2026 08:38:40 +0000 (10:38 +0200)
Add fcpvd{0,1} nodes to the RZ/G3E SoC DTSI.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Link: https://patch.msgid.link/1ba6a98ace4ad9525d054cbaa308d3aeeecfa22a.1775636898.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/r9a09g047.dtsi

index 4267b10937f3f7a8a36d2d4090efe653d6054493..92a3491fb7eac018d81237531f765ace9961fad4 100644 (file)
                                };
                        };
                };
+
+               fcpvd0: fcp@16470000 {
+                       compatible = "renesas,r9a09g047-fcpvd",
+                                    "renesas,fcpv";
+                       reg = <0 0x16470000 0 0x10000>;
+                       clocks = <&cpg CPG_MOD 0xed>,
+                                <&cpg CPG_MOD 0xee>,
+                                <&cpg CPG_MOD 0xef>;
+                       clock-names = "aclk", "pclk", "vclk";
+                       resets = <&cpg 0xdc>;
+                       power-domains = <&cpg>;
+               };
+
+               fcpvd1: fcp@164a0000 {
+                       compatible = "renesas,r9a09g047-fcpvd",
+                                    "renesas,fcpv";
+                       reg = <0 0x164a0000 0 0x10000>;
+                       clocks = <&cpg CPG_MOD 0x1a8>,
+                                <&cpg CPG_MOD 0x1a9>,
+                                <&cpg CPG_MOD 0x1aa>;
+                       clock-names = "aclk", "pclk", "vclk";
+                       resets = <&cpg 0x11e>;
+                       power-domains = <&cpg>;
+               };
        };
 
        stmmac_axi_setup: stmmac-axi-config {