ARM: dts: microchip: sama5d4: Update the cache configuration for CPU

Add the memory size properties for L1 and L2 according with block
diagram from datasheet:

- L1 cache configuration with 32 KB for both data and instruction cache.
- L2 cache configuration with 128 KB unified cache.

[root@sama5d4 ~]$ lscpu
Architecture:             armv7l
  Byte Order:             Little Endian
CPU(s):                   1
  On-line CPU(s) list:    0
Vendor ID:                ARM
  Model name:             Cortex-A5
Caches (sum of all):
  L1d:                    32 KiB (1 instance)
  L1i:                    32 KiB (1 instance)
  L2:                     128 KiB (1 instance)

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250625064934.4828-4-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>

diff --git a/arch/arm/boot/dts/microchip/sama5d4.dtsi b/arch/arm/boot/dts/microchip/sama5d4.dtsi
index 59a7d557c7cb2e218a31d7e9906dd77061359b84..ec1d68c640dea85150c469c48d35dcc7cc4e699a 100644 (file)
--- a/arch/arm/boot/dts/microchip/sama5d4.dtsi
+++ b/arch/arm/boot/dts/microchip/sama5d4.dtsi
@@ -50,6 +50,8 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a5";
                        reg = <0>;
+                       d-cache-size = <0x8000>;        // L1, 32 KB
+                       i-cache-size = <0x8000>;        // L1, 32 KB
                        next-level-cache = <&L2>;
                };
        };
@@ -143,6 +145,7 @@
                        interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
                        cache-unified;
                        cache-level = <2>;
+                       cache-size = <0x20000>;         // L2, 128 KB
                };
 
                ebi: ebi@10000000 {