and maybe some other firmwares.
+2013-11-26 Vladimir Serbinenko <phcoder@gmail.com>
+
+ Add PCI command activation to all PCI drivers as required for coreboot
+ and maybe some other firmwares.
+
2013-11-26 Vladimir Serbinenko <phcoder@gmail.com>
* grub-core/Makefile.am: Reduce gratuituous differences between Apple
"EHCI grub_ehci_pci_iter: registers above 4G are not supported\n");
return 0;
}
+ base &= GRUB_PCI_ADDR_MEM_MASK;
+ if (!base)
+ {
+ grub_dprintf ("ehci",
+ "EHCI: EHCI is not mapped\n");
+ return 0;
+ }
/* Set bus master - needed for coreboot, VMware, broken BIOSes etc. */
addr = grub_pci_make_address (dev, GRUB_PCI_REG_COMMAND);
grub_pci_write_word(addr,
- GRUB_PCI_COMMAND_BUS_MASTER | grub_pci_read_word(addr));
+ GRUB_PCI_COMMAND_MEM_ENABLED
+ | GRUB_PCI_COMMAND_BUS_MASTER
+ | grub_pci_read_word(addr));
grub_dprintf ("ehci", "EHCI grub_ehci_pci_iter: 32-bit EHCI OK\n");
}
addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG0);
base = grub_pci_read (addr);
-#if 0
- /* Stop if there is no IO space base address defined. */
- if (! (base & 1))
- return 0;
-#endif
+ base &= GRUB_PCI_ADDR_MEM_MASK;
+ if (!base)
+ {
+ grub_dprintf ("ehci",
+ "EHCI: EHCI is not mapper\n");
+ return 0;
+ }
/* Set bus master - needed for coreboot, VMware, broken BIOSes etc. */
addr = grub_pci_make_address (dev, GRUB_PCI_REG_COMMAND);
grub_pci_write_word(addr,
- GRUB_PCI_COMMAND_BUS_MASTER | grub_pci_read_word(addr));
+ GRUB_PCI_COMMAND_MEM_ENABLED
+ | GRUB_PCI_COMMAND_BUS_MASTER
+ | grub_pci_read_word(addr));
grub_dprintf ("ohci", "class=0x%02x 0x%02x interface 0x%02x\n",
class, subclass, interf);
if (class != 0x0c || subclass != 0x03 || interf != 0x00)
return 0;
- /* Set bus master - needed for coreboot or broken BIOSes */
- addr = grub_pci_make_address (dev, GRUB_PCI_REG_COMMAND);
- grub_pci_write_word(addr, GRUB_PCI_COMMAND_IO_ENABLED
- | GRUB_PCI_COMMAND_BUS_MASTER
- | grub_pci_read_word (addr));
-
/* Determine IO base address. */
addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG4);
base = grub_pci_read (addr);
if ((base & GRUB_UHCI_IOMASK) == 0)
return 0;
+ /* Set bus master - needed for coreboot or broken BIOSes */
+ addr = grub_pci_make_address (dev, GRUB_PCI_REG_COMMAND);
+ grub_pci_write_word(addr, GRUB_PCI_COMMAND_IO_ENABLED
+ | GRUB_PCI_COMMAND_BUS_MASTER
+ | GRUB_PCI_COMMAND_MEM_ENABLED
+ | grub_pci_read_word (addr));
+
grub_dprintf ("uhci", "base = %x\n", base);
/* Allocate memory for the controller and register it. */
bar2 = grub_pci_read (addr);
/* Check if the BARs describe an IO region. */
- if ((bar1 & 1) && (bar2 & 1))
+ if ((bar1 & 1) && (bar2 & 1) && (bar1 & ~3))
{
rega = bar1 & ~3;
+ addr = grub_pci_make_address (dev, GRUB_PCI_REG_COMMAND);
+ grub_pci_write_word (addr, grub_pci_read_word (addr)
+ | GRUB_PCI_COMMAND_IO_ENABLED
+ | GRUB_PCI_COMMAND_MEM_ENABLED
+ | GRUB_PCI_COMMAND_BUS_MASTER);
+
}
}
if (((class >> 16) & 0xffff) != 0x0300 || pciid != 0x11111234)
return 0;
- *found = 1;
-
addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG0);
framebuffer.base = grub_pci_read (addr) & GRUB_PCI_ADDR_MEM_MASK;
+ if (!framebuffer.base)
+ return 0;
+ *found = 1;
framebuffer.dev = dev;
+ /* Enable address spaces. */
+ addr = grub_pci_make_address (framebuffer.dev, GRUB_PCI_REG_COMMAND);
+ grub_pci_write (addr, 0x7);
+
return 1;
}
if (((class >> 16) & 0xffff) != 0x0300 || pciid != 0x00b81013)
return 0;
-
- *found = 1;
addr = grub_pci_make_address (dev, GRUB_PCI_REG_ADDRESS_REG0);
framebuffer.base = grub_pci_read (addr) & GRUB_PCI_ADDR_MEM_MASK;
+ if (!framebuffer.base)
+ return 0;
+
+ *found = 1;
+
+ /* Enable address spaces. */
+ addr = grub_pci_make_address (framebuffer.dev, GRUB_PCI_REG_COMMAND);
+ grub_pci_write (addr, 0x7);
+
framebuffer.dev = dev;
return 1;