RISC-V: Refine the test case for vector avg_floor and avg_ceil [NFC]

The previous test case doesn't leverage the right test helper macro,
it should be DEF_AVG_0_WRAP instead of DEF_AVG_0.  We prefer the
test function name is test_avg_floor_int64_t_int32_t_0 instead
of test_avg_floor_WT_NT_0 for DEF_AVG_0(WT, NT).

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c:
	Leverage DEF_AVG_0_WRAP to generate the correct func name.
	* gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c
index 138124c8c4a0aa485b998e6b7d7ceef29e794b77..31d3b43de04916f51419b841361f8c20eb1c7308 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c
@@ -6,7 +6,7 @@
 #define NT int16_t
 #define WT int32_t
 
-DEF_AVG_1(NT, WT, avg_ceil)
+DEF_AVG_1_WRAP(NT, WT, avg_ceil)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c
index 30438c90abeacc3b7e70953040d3eb5294c97ca8..7f30b9ec3f1604482a9b73e32251c4f757dc89d2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c
@@ -6,7 +6,7 @@
 #define NT int16_t
 #define WT int64_t
 
-DEF_AVG_1(NT, WT, avg_ceil)
+DEF_AVG_1_WRAP(NT, WT, avg_ceil)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c
index 2e9cfa509403b07058b71c060d4df0023906aed5..2e06d0a3a4648bc4e5597538e034d5e2a7501b5f 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c
@@ -6,7 +6,7 @@
 #define NT int32_t
 #define WT int64_t
 
-DEF_AVG_1(NT, WT, avg_ceil)
+DEF_AVG_1_WRAP(NT, WT, avg_ceil)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c
index 64df06b27e9bf020861b036ac94b281a4980cc89..ca23066275020e48578916a09e699214ca84ca5d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c
@@ -6,7 +6,7 @@
 #define NT int64_t
 #define WT int128_t
 
-DEF_AVG_1(NT, WT, avg_ceil)
+DEF_AVG_1_WRAP(NT, WT, avg_ceil)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c
index 2ebf2945a0eefedb126612de8c6789815f2a3ce3..dda84a6b4379e943ed8a63a9877324bd6c2df1a4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c
@@ -6,7 +6,7 @@
 #define NT int8_t
 #define WT int16_t
 
-DEF_AVG_1(NT, WT, avg_ceil)
+DEF_AVG_1_WRAP(NT, WT, avg_ceil)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c
index 64fec9135b5dca653daefacb1ec063ad6a3e21b8..dfd2bb31357e644668eefd35fedde9ac4f7f910a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c
@@ -6,7 +6,7 @@
 #define NT int8_t
 #define WT int32_t
 
-DEF_AVG_1(NT, WT, avg_ceil)
+DEF_AVG_1_WRAP(NT, WT, avg_ceil)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c
index a72642c9b103eff36ab441bec80dbfbf90c4523c..d1060cc663dbbeb75d07e5ea31bea30314184f78 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c
@@ -6,7 +6,7 @@
 #define NT int8_t
 #define WT int64_t
 
-DEF_AVG_1(NT, WT, avg_ceil)
+DEF_AVG_1_WRAP(NT, WT, avg_ceil)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c
index 16ba96735000ab35f40d3fb45b4b5829c75f1119..fc7943c5e21eb1a1bd2b50368d3392d3b030b159 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c
@@ -6,7 +6,7 @@
 #define NT int16_t
 #define WT int32_t
 
-DEF_AVG_0(NT, WT, avg_floor)
+DEF_AVG_0_WRAP(NT, WT, avg_floor)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c
index b229b4b5703a468db87a81c3774af8ce0b35e01a..e02e5df69c47a6271df51e8e268fd01c29771bb7 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c
@@ -6,7 +6,7 @@
 #define NT int16_t
 #define WT int64_t
 
-DEF_AVG_0(NT, WT, avg_floor)
+DEF_AVG_0_WRAP(NT, WT, avg_floor)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c
index 5f946bbc8cd4a503f3d8c8f378244fc93c60aaac..e36e4242cb0b953bea9f1ef19b0361206a0b6f90 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c
@@ -6,7 +6,7 @@
 #define NT int32_t
 #define WT int64_t
 
-DEF_AVG_0(NT, WT, avg_floor)
+DEF_AVG_0_WRAP(NT, WT, avg_floor)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c
index c94dfc2bde217e33e989716952ef9f1d163d0d31..3e2d97ddad4cd6905b0dc7dc35c7d64e9cac220c 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c
@@ -6,7 +6,7 @@
 #define NT int64_t
 #define WT int128_t
 
-DEF_AVG_0(NT, WT, avg_floor)
+DEF_AVG_0_WRAP(NT, WT, avg_floor)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c
index 5d9297a6c394c22c27f1a0623b36a025b4d8fe38..cdbb2999183a3be4a2201d912162ea9155489d6d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c
@@ -6,7 +6,7 @@
 #define NT int8_t
 #define WT int16_t
 
-DEF_AVG_0(NT, WT, avg_floor)
+DEF_AVG_0_WRAP(NT, WT, avg_floor)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c
index 5c5d4ea40bb1c88a2db00688c76bf6c7a3f0547b..53508b09ac3972fa88fcb91e1ac0633808d1980e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c
@@ -6,7 +6,7 @@
 #define NT int8_t
 #define WT int32_t
 
-DEF_AVG_0(NT, WT, avg_floor)
+DEF_AVG_0_WRAP(NT, WT, avg_floor)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c
index f297953aadf470fa46130058fbcec5c62e3dd4ba..9a6d1a21e52fea0a5842fb3147236b5531648cf4 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c
@@ -6,7 +6,7 @@
 #define NT int8_t
 #define WT int64_t
 
-DEF_AVG_0(NT, WT, avg_floor)
+DEF_AVG_0_WRAP(NT, WT, avg_floor)
 
 /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */
 /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */