]> git.ipfire.org Git - thirdparty/glibc.git/commitdiff
Add arch-specific configuration for C11 atomics support.
authorTorvald Riegel <triegel@redhat.com>
Fri, 17 Oct 2014 23:02:59 +0000 (01:02 +0200)
committerTorvald Riegel <triegel@redhat.com>
Thu, 20 Nov 2014 10:57:38 +0000 (11:57 +0100)
This sets __HAVE_64B_ATOMICS if provided.  It also sets
USE_ATOMIC_COMPILER_BUILTINS to true if the existing atomic ops use the
__atomic* builtins (aarch64, mips partially) or if this has been
tested (x86_64); otherwise, this is set to false so that C11 atomics will
be based on the existing atomic operations.

22 files changed:
ChangeLog
sysdeps/aarch64/bits/atomic.h
sysdeps/alpha/bits/atomic.h
sysdeps/arm/bits/atomic.h
sysdeps/i386/i486/bits/atomic.h
sysdeps/ia64/bits/atomic.h
sysdeps/m68k/coldfire/bits/atomic.h
sysdeps/m68k/m680x0/m68020/bits/atomic.h
sysdeps/microblaze/bits/atomic.h
sysdeps/mips/bits/atomic.h
sysdeps/powerpc/powerpc32/bits/atomic.h
sysdeps/powerpc/powerpc64/bits/atomic.h
sysdeps/s390/bits/atomic.h
sysdeps/sparc/sparc32/bits/atomic.h
sysdeps/sparc/sparc32/sparcv9/bits/atomic.h
sysdeps/sparc/sparc64/bits/atomic.h
sysdeps/tile/tilegx/bits/atomic.h
sysdeps/tile/tilepro/bits/atomic.h
sysdeps/unix/sysv/linux/hppa/bits/atomic.h
sysdeps/unix/sysv/linux/m68k/coldfire/bits/atomic.h
sysdeps/unix/sysv/linux/sh/bits/atomic.h
sysdeps/x86_64/bits/atomic.h

index 6199b7e692da79e4777a28037f79e144754156b6..cf1b12209219593c3b5ba7290e39532051df7b00 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,48 @@
+2014-11-20  Torvald Riegel  <triegel@redhat.com>
+
+       * sysdeps/aarch64/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Define.
+       * sysdeps/alpha/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/arm/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/i386/i486/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/ia64/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/m68k/coldfire/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/m68k/m680x0/m68020/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/microblaze/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/mips/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/powerpc/powerpc32/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/powerpc/powerpc64/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/s390/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/sparc/sparc32/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/sparc/sparc32/sparcv9/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/sparc/sparc64/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/tile/tilegx/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/tile/tilepro/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/unix/sysv/linux/hppa/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/unix/sysv/linux/m68k/coldfire/bits/atomic.h
+       (__HAVE_64B_ATOMICS, USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/unix/sysv/linux/sh/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+       * sysdeps/x86_64/bits/atomic.h (__HAVE_64B_ATOMICS,
+       USE_ATOMIC_COMPILER_BUILTINS): Likewise.
+
 2014-11-19  Roland McGrath  <roland@hack.frob.com>
 
        * nptl/pthread_create.c (__pthread_create_2_1): Don't try to validate
index 456e2ecdffcb8f167188cad2f73e234bba842554..a8d3ae721f93b70bfc463f700868b550bef239fc 100644 (file)
@@ -36,6 +36,8 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 1
 
 /* Compare and exchange.
    For all "bool" routines, we return FALSE if exchange succesful.  */
index abbbc7c92d9617e3412777bc8bd853985362a478..e9275e998238b7c8910a7b765b44a927db564ee4 100644 (file)
@@ -42,6 +42,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #ifdef UP
 # define __MB          /* nothing */
index 88cbe679267ea5c1449c16d6ab9e6cf2d9743bea..315b4cf603c5fcfbd9c26f796a31803d64429224 100644 (file)
@@ -33,6 +33,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 void __arm_link_error (void);
 
 #ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
index 76e0e8e2e34880a03abbd916110c7e64a1bcafc4..739d3846f2fe9ebecf29181b1cdafb3ab4acc74f 100644 (file)
@@ -54,6 +54,9 @@ typedef uintmax_t uatomic_max_t;
 # endif
 #endif
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
   __sync_val_compare_and_swap (mem, oldval, newval)
index 766cb4b7415a8d790f20cb5530995054e83c80ea..5e090b9072b9504877323bc7bc5776997e8420e0 100644 (file)
@@ -43,6 +43,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
   (abort (), 0)
index ec0c59a7da6234d9c4116bd526a27895b6eb8a6f..4851999fcaeec53f387edbfda7ba3bb779c6082c 100644 (file)
@@ -49,6 +49,10 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+/* If we have just non-atomic operations, we can as well make them wide.  */
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* The only basic operation needed is compare and exchange.  */
 #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
   ({ __typeof (mem) __gmemp = (mem);                                 \
index 0f081f169a8001cb36b41b8983a57297bf216c5c..395bac06b97203d7ca103b9b523515afd9ceecfc 100644 (file)
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
   ({ __typeof (*(mem)) __ret;                                                \
      __asm __volatile ("cas%.b %0,%2,%1"                                     \
index 77004a0284b2dc539de0ab9af4bca193a2c91edc..395162df2dee6e26ca6ad731486b84bc1ec46683 100644 (file)
@@ -35,6 +35,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 /* Microblaze does not have byte and halfword forms of load and reserve and
    store conditional. So for microblaze we stub out the 8- and 16-bit forms.  */
index 35b378678906bdbffc7d09a2abf75f4f6e61486f..091b199bf8b543d214d40bacfe2124f2b594ee6d 100644 (file)
@@ -44,6 +44,12 @@ typedef uintmax_t uatomic_max_t;
 #define MIPS_PUSH_MIPS2
 #endif
 
+#if _MIPS_SIM == _ABIO32
+#define __HAVE_64B_ATOMICS 0
+#else
+#define __HAVE_64B_ATOMICS 1
+#endif
+
 /* See the comments in <sys/asm.h> about the use of the sync instruction.  */
 #ifndef MIPS_SYNC
 # define MIPS_SYNC     sync
@@ -86,6 +92,8 @@ typedef uintmax_t uatomic_max_t;
    have no assembly alternative available and want to avoid the __sync_*
    builtins if at all possible.  */
 
+#define USE_ATOMIC_COMPILER_BUILTINS 1
+
 /* Compare and exchange.
    For all "bool" routines, we return FALSE if exchange succesful.  */
 
@@ -234,6 +242,8 @@ typedef uintmax_t uatomic_max_t;
 /* This implementation using inline assembly will be removed once glibc
    requires GCC 4.8 or later to build.  */
 
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* Compare and exchange.  For all of the "xxx" routines, we expect a
    "__prev" and a "__cmp" variable to be provided by the enclosing scope,
    in which values are returned.  */
index a3dd09cd9a626ee4ab268be3ef48568f8ccdba4f..117b5a077515cd758ae3cd59bd28c74fb8174ada 100644 (file)
@@ -33,6 +33,9 @@
 # define MUTEX_HINT_REL
 #endif
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /*
  * The 32-bit exchange_bool is different on powerpc64 because the subf
  * does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
index ed26b7253e31cb91cfd74b342ed601ce1ba99cee..5c4ebb6ad530874d3ba580d3e036aa8257f8e2ad 100644 (file)
@@ -33,6 +33,9 @@
 # define MUTEX_HINT_REL
 #endif
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* The 32-bit exchange_bool is different on powerpc64 because the subf
    does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
    (a load word and zero (high 32) form) load.
index 682416577950090e8bcb899f6a56ba34a86e200b..b809b5efaa6e6feeadc81cf4682efa5d1ae049e8 100644 (file)
@@ -43,6 +43,8 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
   (abort (), (__typeof (*mem)) 0)
@@ -59,6 +61,7 @@ typedef uintmax_t uatomic_max_t;
      __archold; })
 
 #ifdef __s390x__
+# define __HAVE_64B_ATOMICS 1
 # define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
   ({ __typeof (mem) __archmem = (mem);                                       \
      __typeof (*mem) __archold = (oldval);                                   \
@@ -67,6 +70,7 @@ typedef uintmax_t uatomic_max_t;
                       : "d" ((long) (newval)), "m" (*__archmem) : "cc", "memory" );    \
      __archold; })
 #else
+# define __HAVE_64B_ATOMICS 0
 /* For 31 bit we do not really need 64-bit compare-and-exchange. We can
    implement them by use of the csd instruction. The straightforward
    implementation causes warnings so we skip the definition for now.  */
index 251e65662d61c3997a35073b0e8d8eff479f46cf..2ae2eaa553e4d77d6c8298c2d282ac8d1b35e5cc 100644 (file)
@@ -47,6 +47,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 /* We have no compare and swap, just test and set.
    The following implementation contends on 64 global locks
index 310e6365e9daa4b34bd3a18c9053005275abb112..7644796da9bb926f32800d13eb45277115adb16a 100644 (file)
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
   (abort (), (__typeof (*mem)) 0)
index d348ed20ae2b140aa9c06831510515a8b07cf997..2bca42b0516e62195558556597fa9e4ac756cfd7 100644 (file)
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 
 #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
   (abort (), (__typeof (*mem)) 0)
index ce12db021605f210c52a772a9bb6374d80dc4828..9aa299f03b817a03db46b468ba4c02ba5b55b77b 100644 (file)
@@ -21,6 +21,9 @@
 
 #include <arch/spr_def.h>
 
+#define __HAVE_64B_ATOMICS 1
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* Pick appropriate 8- or 4-byte instruction. */
 #define __atomic_update(mem, v, op)                                     \
   ((__typeof (*(mem))) (__typeof (*(mem) - *(mem)))                     \
index cbbf64cef1f4be4298c8ddaee5d7f950745d5cd0..c3865bee2f550f14972da227f7ee79fc019273b4 100644 (file)
@@ -21,6 +21,9 @@
 
 #include <asm/unistd.h>
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* 32-bit integer compare-and-exchange. */
 static __inline __attribute__ ((always_inline))
 int __atomic_cmpxchg_32 (volatile int *mem, int newval, int oldval)
index e55e91b3524251f013d0a9ea448e99db807c5c88..b5cdfb649562e65606a55157fc9b53909f21eb0e 100644 (file)
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* prev = *addr;
    if (prev == old)
      *addr = new;
index cd9bae324e71b487e1303fb6f0851fe746fa35ff..a8d4a33d5a017517e24441c0dde51f6f5c50a130 100644 (file)
@@ -36,6 +36,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* The only basic operation needed is compare and exchange.  */
 /* For ColdFire we'll have to trap into the kernel mode anyway,
    so trap from the library rather then from the kernel wrapper.  */
index e81941200736503afd1fd9cf8f6d9877f6f9a73b..6508c33342bd5e716121033eb5c4b919a21f6da5 100644 (file)
@@ -44,6 +44,9 @@ typedef uintptr_t uatomicptr_t;
 typedef intmax_t atomic_max_t;
 typedef uintmax_t uatomic_max_t;
 
+#define __HAVE_64B_ATOMICS 0
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+
 /* SH kernel has implemented a gUSA ("g" User Space Atomicity) support
    for the user space atomicity. The atomicity macros use this scheme.
 
index 4d19ef0bb4fda831ea3a27e5e28eb48a6de373e3..99dfb50295019132f5729f405f7abbf94c874ea3 100644 (file)
@@ -55,6 +55,12 @@ typedef uintmax_t uatomic_max_t;
 # endif
 #endif
 
+#define __HAVE_64B_ATOMICS 1
+#if __GNUC_PREREQ (4, 7)
+#define USE_ATOMIC_COMPILER_BUILTINS 1
+#else
+#define USE_ATOMIC_COMPILER_BUILTINS 0
+#endif
 
 #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
   __sync_val_compare_and_swap (mem, oldval, newval)