Track vex r2001 (initial PCMPISTRI support):

* handle new pseudo-reg XMM16 in memcheck/mc_machine.c

* run_thread_for_a_while: assert that the amd64 XMM guest reg array
  has no holes and the elements are the right size, so that the
  (PCMP)ISTRI_* helpers can treat it as an array.

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@11249

diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c
index f9df2421cd0a77a9290c16575ccf820e59eca3e4..4716cf48e40ab65718cd8d1a327a744cca58b3f9 100644 (file)
--- a/coregrind/m_scheduler/scheduler.c
+++ b/coregrind/m_scheduler/scheduler.c
@@ -644,6 +644,16 @@ static void do_pre_run_checks ( ThreadState* tst )
    vg_assert(sz_spill == LibVEX_N_SPILL_BYTES);
    vg_assert(a_vex + 3 * sz_vex == a_spill);
 
+#  if defined(VGA_amd64)
+   /* x86/amd64 XMM regs must form an array, ie, have no
+      holes in between. */
+   vg_assert(
+      (offsetof(VexGuestAMD64State,guest_XMM16)
+       - offsetof(VexGuestAMD64State,guest_XMM0))
+      == (17/*#regs*/-1) * 16/*bytes per reg*/
+   );
+#  endif
+
 #  if defined(VGA_ppc32) || defined(VGA_ppc64)
    /* ppc guest_state vector regs must be 16 byte aligned for
       loads/stores.  This is important! */
@@ -654,7 +664,7 @@ static void do_pre_run_checks ( ThreadState* tst )
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VR1));
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow1.guest_VR1));
    vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex_shadow2.guest_VR1));
-#  endif   
+#  endif
 
 #  if defined(VGA_arm)
    /* arm guest_state VFP regs must be 8 byte aligned for

diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
index 823e7ae2f8e1a9ab41aa12cafc6f221842f15c90..30995237769c133ff4fd0244fd506871f41b57e8 100644 (file)
--- a/memcheck/mc_machine.c
+++ b/memcheck/mc_machine.c
@@ -536,6 +536,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
    if (o >= GOF(XMM13) && o+sz <= GOF(XMM13)+SZB(XMM13)) return GOF(XMM13);
    if (o >= GOF(XMM14) && o+sz <= GOF(XMM14)+SZB(XMM14)) return GOF(XMM14);
    if (o >= GOF(XMM15) && o+sz <= GOF(XMM15)+SZB(XMM15)) return GOF(XMM15);
+   if (o >= GOF(XMM16) && o+sz <= GOF(XMM16)+SZB(XMM16)) return GOF(XMM16);
 
    /* MMX accesses to FP regs.  Need to allow for 32-bit references
       due to dirty helpers for frstor etc, which reference the entire