drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY

Try HDMI PLL alogorithm for C10 PHY, if there are no pre-computed tables.
Also get rid of the helpers to get rate for HDMI for C10/20 PHY, as we no
longer depend only on pre-computed tables.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250120042122.1029481-6-ankit.k.nautiyal@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 857262fcbac9f493cf1b254bf6c955673d1ea4bb..39c98549ac4ea063b36b011fd37f2c2ca3518280 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -18,6 +18,7 @@
 #include "intel_hdmi.h"
 #include "intel_panel.h"
 #include "intel_psr.h"
+#include "intel_snps_hdmi_pll.h"
 #include "intel_tc.h"
 
 #define MB_WRITE_COMMITTED      true
@@ -2003,19 +2004,6 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
        NULL,
 };
 
-static int intel_c10_phy_check_hdmi_link_rate(int clock)
-{
-       const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
-       int i;
-
-       for (i = 0; tables[i]; i++) {
-               if (clock == tables[i]->clock)
-                       return MODE_OK;
-       }
-
-       return MODE_CLOCK_RANGE;
-}
-
 static const struct intel_c10pll_state * const *
 intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
                        struct intel_encoder *encoder)
@@ -2077,6 +2065,16 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
                }
        }
 
+       /* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */
+       if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
+               intel_snps_hdmi_pll_compute_c10pll(&crtc_state->dpll_hw_state.cx0pll.c10,
+                                                  crtc_state->port_clock);
+               intel_c10pll_update_pll(crtc_state, encoder);
+               crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
+
+               return 0;
+       }
+
        return -EINVAL;
 }
 
@@ -2281,31 +2279,6 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
        return 0;
 }
 
-static int intel_c20_phy_check_hdmi_link_rate(int clock)
-{
-       const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
-       int i;
-
-       for (i = 0; tables[i]; i++) {
-               if (clock == tables[i]->clock)
-                       return MODE_OK;
-       }
-
-       if (clock >= 25175 && clock <= 594000)
-               return MODE_OK;
-
-       return MODE_CLOCK_RANGE;
-}
-
-int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock)
-{
-       struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
-
-       if (intel_encoder_is_c10phy(&dig_port->base))
-               return intel_c10_phy_check_hdmi_link_rate(clock);
-       return intel_c20_phy_check_hdmi_link_rate(clock);
-}
-
 static const struct intel_c20pll_state * const *
 intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
                         struct intel_encoder *encoder)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 7111688826849d18ef336ec2e0b320b3405f8153..573fa7d3e88fecc5f03671da25a5ffe3d9d25fd6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -41,7 +41,6 @@ bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
                                   const struct intel_cx0pll_state *b);
 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
                                     const struct intel_crtc_state *crtc_state);
-int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
 
 #endif /* __INTEL_CX0_PHY_H__ */

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index a0133713725be541f81d038a11376a8d3fd0d451..95584b61cf08886c40ef0050816a09918cd19ab9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1909,16 +1909,6 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
        if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800)
                return MODE_CLOCK_RANGE;
 
-       /*
-        * SNPS PHYs' MPLLB table-based programming can only handle a fixed
-        * set of link rates.
-        *
-        * FIXME: We will hopefully get an algorithmic way of programming
-        * the MPLLB for HDMI in the future.
-        */
-       if (DISPLAY_VER(display) >= 14)
-               return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
-
        return MODE_OK;
 }