drm/amd: Disable PP_PCIE_DPM_MASK when dynamic speed switching not supported

[ Upstream commit fbf1035b033a51eee48d5f42e781b02fff272ca0 ]

Rather than individual ASICs checking for the quirk, set the quirk at the
driver level.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index ecc61a6d13e13ac421953f213f63e51bbfb0eed7..65779cbdbad13c8783fd442b5eb36081ea91480b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2318,6 +2318,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
                adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
        if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
                adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
+       if (!amdgpu_device_pcie_dynamic_switching_supported())
+               adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;
 
        total = true;
        for (i = 0; i < adev->num_ip_blocks; i++) {

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 1cb40226449779d004d9cf2fdfae8e7f7f1364c0..a38888176805d584da9c0a3ebff3ac72976c3516 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1823,9 +1823,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 
        data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
        data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
-       data->pcie_dpm_key_disabled =
-               !amdgpu_device_pcie_dynamic_switching_supported() ||
-               !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
+       data->pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
        /* need to set voltage control types before EVV patching */
        data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
        data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 9a5f3d31e77806ba094c23f4e8d365126b7e6f77..94f22df5ac2050245545fc424f990073b4f33213 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2107,7 +2107,7 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
        min_lane_width = min_lane_width > max_lane_width ?
                         max_lane_width : min_lane_width;
 
-       if (!amdgpu_device_pcie_dynamic_switching_supported()) {
+       if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
                pcie_table->pcie_gen[0] = max_gen_speed;
                pcie_table->pcie_lane[0] = max_lane_width;
        } else {

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 4fa94f583b87cafc97a9aa2e6c36611033c4a9a8..223e890575a2bdd7d07f1e93fea53b05626320d9 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2436,7 +2436,7 @@ int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
        uint32_t smu_pcie_arg;
        int ret, i;
 
-       if (!amdgpu_device_pcie_dynamic_switching_supported()) {
+       if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
                if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
                        pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];