uint32_t test_flags)
{
volatile uint32_t res, flags, xer, xer_orig, tmpcr, tmpxer;
- int i, j;
+ int i, j, is_div;
+
+ // catches div, divwu, divo, divwu, divwuo, and . variants
+ is_div = NULL != strstr(name, "divw");
xer_orig = 0x00000000;
redo:
for (j=0; j<nb_iargs; j++) {
r14 = iargs[i];
r15 = iargs[j];
+ /* result of division by zero is implementation dependent.
+ don't test it. */
+ if (is_div && iargs[j] == 0)
+ continue;
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
}
if (verbose) printf("\n");
}
- if (test_flags & PPC_XER_CA && xer_orig == 0x00000000) {
+ if ((test_flags & PPC_XER_CA) && xer_orig == 0x00000000) {
xer_orig = 0x20000000;
goto redo;
}
printf("%s %08x => %08x (%08x %08x)\n",
name, iargs[i], res, flags, xer);
}
- if (test_flags & PPC_XER_CA && xer_orig == 0x00000000) {
+ if ((test_flags & PPC_XER_CA) && xer_orig == 0x00000000) {
xer_orig = 0x20000000;
goto redo;
}
addco ffffffff, 000f423f => 000f423e (00000000 20000000)
addco ffffffff, ffffffff => fffffffe (00000000 20000000)
- divw 00000000, 00000000 => 00000000 (00000000 00000000)
divw 00000000, 000f423f => 00000000 (00000000 00000000)
divw 00000000, ffffffff => 00000000 (00000000 00000000)
- divw 000f423f, 00000000 => 00000000 (00000000 00000000)
divw 000f423f, 000f423f => 00000001 (00000000 00000000)
divw 000f423f, ffffffff => fff0bdc1 (00000000 00000000)
- divw ffffffff, 00000000 => 00000000 (00000000 00000000)
divw ffffffff, 000f423f => 00000000 (00000000 00000000)
divw ffffffff, ffffffff => 00000001 (00000000 00000000)
- divwo 00000000, 00000000 => 00000000 (00000000 c0000000)
divwo 00000000, 000f423f => 00000000 (00000000 00000000)
divwo 00000000, ffffffff => 00000000 (00000000 00000000)
- divwo 000f423f, 00000000 => 00000000 (00000000 c0000000)
divwo 000f423f, 000f423f => 00000001 (00000000 00000000)
divwo 000f423f, ffffffff => fff0bdc1 (00000000 00000000)
- divwo ffffffff, 00000000 => 00000000 (00000000 c0000000)
divwo ffffffff, 000f423f => 00000000 (00000000 00000000)
divwo ffffffff, ffffffff => 00000001 (00000000 00000000)
- divwu 00000000, 00000000 => 00000000 (00000000 00000000)
divwu 00000000, 000f423f => 00000000 (00000000 00000000)
divwu 00000000, ffffffff => 00000000 (00000000 00000000)
- divwu 000f423f, 00000000 => 00000000 (00000000 00000000)
divwu 000f423f, 000f423f => 00000001 (00000000 00000000)
divwu 000f423f, ffffffff => 00000000 (00000000 00000000)
- divwu ffffffff, 00000000 => 00000000 (00000000 00000000)
divwu ffffffff, 000f423f => 000010c6 (00000000 00000000)
divwu ffffffff, ffffffff => 00000001 (00000000 00000000)
- divwuo 00000000, 00000000 => 00000000 (00000000 c0000000)
divwuo 00000000, 000f423f => 00000000 (00000000 00000000)
divwuo 00000000, ffffffff => 00000000 (00000000 00000000)
- divwuo 000f423f, 00000000 => 00000000 (00000000 c0000000)
divwuo 000f423f, 000f423f => 00000001 (00000000 00000000)
divwuo 000f423f, ffffffff => 00000000 (00000000 00000000)
- divwuo ffffffff, 00000000 => 00000000 (00000000 c0000000)
divwuo ffffffff, 000f423f => 000010c6 (00000000 00000000)
divwuo ffffffff, ffffffff => 00000001 (00000000 00000000)
addco. ffffffff, 000f423f => 000f423e (40000000 20000000)
addco. ffffffff, ffffffff => fffffffe (80000000 20000000)
- divw. 00000000, 00000000 => 00000000 (20000000 00000000)
divw. 00000000, 000f423f => 00000000 (20000000 00000000)
divw. 00000000, ffffffff => 00000000 (20000000 00000000)
- divw. 000f423f, 00000000 => 00000000 (20000000 00000000)
divw. 000f423f, 000f423f => 00000001 (40000000 00000000)
divw. 000f423f, ffffffff => fff0bdc1 (80000000 00000000)
- divw. ffffffff, 00000000 => 00000000 (20000000 00000000)
divw. ffffffff, 000f423f => 00000000 (20000000 00000000)
divw. ffffffff, ffffffff => 00000001 (40000000 00000000)
- divwo. 00000000, 00000000 => 00000000 (30000000 c0000000)
divwo. 00000000, 000f423f => 00000000 (20000000 00000000)
divwo. 00000000, ffffffff => 00000000 (20000000 00000000)
- divwo. 000f423f, 00000000 => 00000000 (30000000 c0000000)
divwo. 000f423f, 000f423f => 00000001 (40000000 00000000)
divwo. 000f423f, ffffffff => fff0bdc1 (80000000 00000000)
- divwo. ffffffff, 00000000 => 00000000 (30000000 c0000000)
divwo. ffffffff, 000f423f => 00000000 (20000000 00000000)
divwo. ffffffff, ffffffff => 00000001 (40000000 00000000)
- divwu. 00000000, 00000000 => 00000000 (20000000 00000000)
divwu. 00000000, 000f423f => 00000000 (20000000 00000000)
divwu. 00000000, ffffffff => 00000000 (20000000 00000000)
- divwu. 000f423f, 00000000 => 00000000 (20000000 00000000)
divwu. 000f423f, 000f423f => 00000001 (40000000 00000000)
divwu. 000f423f, ffffffff => 00000000 (20000000 00000000)
- divwu. ffffffff, 00000000 => 00000000 (20000000 00000000)
divwu. ffffffff, 000f423f => 000010c6 (40000000 00000000)
divwu. ffffffff, ffffffff => 00000001 (40000000 00000000)
- divwuo. 00000000, 00000000 => 00000000 (30000000 c0000000)
divwuo. 00000000, 000f423f => 00000000 (20000000 00000000)
divwuo. 00000000, ffffffff => 00000000 (20000000 00000000)
- divwuo. 000f423f, 00000000 => 00000000 (30000000 c0000000)
divwuo. 000f423f, 000f423f => 00000001 (40000000 00000000)
divwuo. 000f423f, ffffffff => 00000000 (20000000 00000000)
- divwuo. ffffffff, 00000000 => 00000000 (30000000 c0000000)
divwuo. ffffffff, 000f423f => 000010c6 (40000000 00000000)
divwuo. ffffffff, ffffffff => 00000001 (40000000 00000000)
addco ffffffff, 000f423f => 000f423e (00000000 20000000)
addco ffffffff, ffffffff => fffffffe (00000000 20000000)
- divw 00000000, 00000000 => 00000000 (00000000 00000000)
divw 00000000, 000f423f => 00000000 (00000000 00000000)
divw 00000000, ffffffff => 00000000 (00000000 00000000)
- divw 000f423f, 00000000 => 00000000 (00000000 00000000)
divw 000f423f, 000f423f => 00000001 (00000000 00000000)
divw 000f423f, ffffffff => fff0bdc1 (00000000 00000000)
- divw ffffffff, 00000000 => 00000000 (00000000 00000000)
divw ffffffff, 000f423f => 00000000 (00000000 00000000)
divw ffffffff, ffffffff => 00000001 (00000000 00000000)
- divwo 00000000, 00000000 => 00000000 (00000000 c0000000)
divwo 00000000, 000f423f => 00000000 (00000000 00000000)
divwo 00000000, ffffffff => 00000000 (00000000 00000000)
- divwo 000f423f, 00000000 => 00000000 (00000000 c0000000)
divwo 000f423f, 000f423f => 00000001 (00000000 00000000)
divwo 000f423f, ffffffff => fff0bdc1 (00000000 00000000)
- divwo ffffffff, 00000000 => 00000000 (00000000 c0000000)
divwo ffffffff, 000f423f => 00000000 (00000000 00000000)
divwo ffffffff, ffffffff => 00000001 (00000000 00000000)
- divwu 00000000, 00000000 => 00000000 (00000000 00000000)
divwu 00000000, 000f423f => 00000000 (00000000 00000000)
divwu 00000000, ffffffff => 00000000 (00000000 00000000)
- divwu 000f423f, 00000000 => 00000000 (00000000 00000000)
divwu 000f423f, 000f423f => 00000001 (00000000 00000000)
divwu 000f423f, ffffffff => 00000000 (00000000 00000000)
- divwu ffffffff, 00000000 => 00000000 (00000000 00000000)
divwu ffffffff, 000f423f => 000010c6 (00000000 00000000)
divwu ffffffff, ffffffff => 00000001 (00000000 00000000)
- divwuo 00000000, 00000000 => 00000000 (00000000 c0000000)
divwuo 00000000, 000f423f => 00000000 (00000000 00000000)
divwuo 00000000, ffffffff => 00000000 (00000000 00000000)
- divwuo 000f423f, 00000000 => 00000000 (00000000 c0000000)
divwuo 000f423f, 000f423f => 00000001 (00000000 00000000)
divwuo 000f423f, ffffffff => 00000000 (00000000 00000000)
- divwuo ffffffff, 00000000 => 00000000 (00000000 c0000000)
divwuo ffffffff, 000f423f => 000010c6 (00000000 00000000)
divwuo ffffffff, ffffffff => 00000001 (00000000 00000000)
addco. ffffffff, 000f423f => 000f423e (40000000 20000000)
addco. ffffffff, ffffffff => fffffffe (80000000 20000000)
- divw. 00000000, 00000000 => 00000000 (20000000 00000000)
divw. 00000000, 000f423f => 00000000 (20000000 00000000)
divw. 00000000, ffffffff => 00000000 (20000000 00000000)
- divw. 000f423f, 00000000 => 00000000 (20000000 00000000)
divw. 000f423f, 000f423f => 00000001 (40000000 00000000)
divw. 000f423f, ffffffff => fff0bdc1 (80000000 00000000)
- divw. ffffffff, 00000000 => 00000000 (20000000 00000000)
divw. ffffffff, 000f423f => 00000000 (20000000 00000000)
divw. ffffffff, ffffffff => 00000001 (40000000 00000000)
- divwo. 00000000, 00000000 => 00000000 (30000000 c0000000)
divwo. 00000000, 000f423f => 00000000 (20000000 00000000)
divwo. 00000000, ffffffff => 00000000 (20000000 00000000)
- divwo. 000f423f, 00000000 => 00000000 (30000000 c0000000)
divwo. 000f423f, 000f423f => 00000001 (40000000 00000000)
divwo. 000f423f, ffffffff => fff0bdc1 (80000000 00000000)
- divwo. ffffffff, 00000000 => 00000000 (30000000 c0000000)
divwo. ffffffff, 000f423f => 00000000 (20000000 00000000)
divwo. ffffffff, ffffffff => 00000001 (40000000 00000000)
- divwu. 00000000, 00000000 => 00000000 (20000000 00000000)
divwu. 00000000, 000f423f => 00000000 (20000000 00000000)
divwu. 00000000, ffffffff => 00000000 (20000000 00000000)
- divwu. 000f423f, 00000000 => 00000000 (20000000 00000000)
divwu. 000f423f, 000f423f => 00000001 (40000000 00000000)
divwu. 000f423f, ffffffff => 00000000 (20000000 00000000)
- divwu. ffffffff, 00000000 => 00000000 (20000000 00000000)
divwu. ffffffff, 000f423f => 000010c6 (40000000 00000000)
divwu. ffffffff, ffffffff => 00000001 (40000000 00000000)
- divwuo. 00000000, 00000000 => 00000000 (30000000 c0000000)
divwuo. 00000000, 000f423f => 00000000 (20000000 00000000)
divwuo. 00000000, ffffffff => 00000000 (20000000 00000000)
- divwuo. 000f423f, 00000000 => 00000000 (30000000 c0000000)
divwuo. 000f423f, 000f423f => 00000001 (40000000 00000000)
divwuo. 000f423f, ffffffff => 00000000 (20000000 00000000)
- divwuo. ffffffff, 00000000 => 00000000 (30000000 c0000000)
divwuo. ffffffff, 000f423f => 000010c6 (40000000 00000000)
divwuo. ffffffff, ffffffff => 00000001 (40000000 00000000)