net/mlx5: Add IFC bits for PCIe Congestion Event object

Add definitions for the PCIe Congestion Event object
and the relevant FW command structures.

Signed-off-by: Dragos Tatulea <dtatulea@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Mark Bloch <mbloch@nvidia.com>
Link: https://patch.msgid.link/20250619113721.60201-3-mbloch@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 5c8f75605eacd3b7f654874baf89a0a5ce0e23e9..0e93f342be099c075c7ecc5e16446d35c35c1762 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -12509,6 +12509,7 @@ enum {
        MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
        MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
        MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53,
+       MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58,
        MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
 };
 
@@ -12526,6 +12527,8 @@ enum {
 enum {
        MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL =
                BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40),
+       MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT =
+               BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40),
 };
 
 enum {
@@ -13284,4 +13287,41 @@ struct mlx5_ifc_mrtcq_reg_bits {
        u8         reserved_at_80[0x180];
 };
 
+struct mlx5_ifc_pcie_cong_event_obj_bits {
+       u8         modify_select_field[0x40];
+
+       u8         inbound_event_en[0x1];
+       u8         outbound_event_en[0x1];
+       u8         reserved_at_42[0x1e];
+
+       u8         reserved_at_60[0x1];
+       u8         inbound_cong_state[0x3];
+       u8         reserved_at_64[0x1];
+       u8         outbound_cong_state[0x3];
+       u8         reserved_at_68[0x18];
+
+       u8         inbound_cong_low_threshold[0x10];
+       u8         inbound_cong_high_threshold[0x10];
+
+       u8         outbound_cong_low_threshold[0x10];
+       u8         outbound_cong_high_threshold[0x10];
+
+       u8         reserved_at_e0[0x340];
+};
+
+struct mlx5_ifc_pcie_cong_event_cmd_in_bits {
+       struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
+       struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
+};
+
+struct mlx5_ifc_pcie_cong_event_cmd_out_bits {
+       struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr;
+       struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
+};
+
+enum mlx5e_pcie_cong_event_mod_field {
+       MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0),
+       MLX5_PCIE_CONG_EVENT_MOD_THRESH   = BIT(2),
+};
+
 #endif /* MLX5_IFC_H */