};
};
+ dummy-sink {
+ compatible = "arm,coresight-dummy-sink";
+
+ in-ports {
+ port {
+ eud_in: endpoint {
+ remote-endpoint = <&swao_rep_out1>;
+ };
+ };
+ };
+ };
+
firmware {
scm: scm {
compatible = "qcom,scm-glymur", "qcom,scm";
};
};
- apps_smmu: iommu@15000000 {
- compatible = "qcom,glymur-smmu-500",
- "qcom,smmu-500",
- "arm,mmu-500";
- reg = <0x0 0x15000000 0x0 0x100000>;
-
- #iommu-cells = <2>;
- #global-interrupts = <1>;
-
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+ stm: stm@10002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x0 0x10002000 0x0 0x1000>,
+ <0x0 0x16280000 0x0 0x180000>;
+ reg-names = "stm-base",
+ "stm-stimulus-base";
- dma-coherent;
- };
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
- pcie_smmu: iommu@15480000 {
- compatible = "arm,smmu-v3";
- reg = <0x0 0x15480000 0x0 0x20000>;
- interrupts = <GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 962 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "eventq", "cmdq-sync", "gerror";
- dma-coherent;
- #iommu-cells = <1>;
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel0_in7>;
+ };
+ };
+ };
};
- intc: interrupt-controller@17000000 {
- compatible = "arm,gic-v3";
- reg = <0x0 0x17000000 0x0 0x10000>,
- <0x0 0x17080000 0x0 0x480000>;
+ tpda@10004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10004000 0x0 0x1000>;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
- #interrupt-cells = <3>;
- interrupt-controller;
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ port@1 {
+ reg = <1>;
- gic_its: msi-controller@17040000 {
- compatible = "arm,gic-v3-its";
- reg = <0x0 0x17040000 0x0 0x40000>;
+ qdss_tpda_in1: endpoint {
+ remote-endpoint = <&spdm_tpdm_out>;
+ };
+ };
+ };
- msi-controller;
- #msi-cells = <1>;
+ out-ports {
+ port {
+ qdss_tpda_out: endpoint {
+ remote-endpoint = <&funnel0_in6>;
+ };
+ };
};
};
- watchdog@17600000 {
- compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt";
- reg = <0x0 0x17600000 0x0 0x1000>;
- clocks = <&sleep_clk>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
- };
+ tpdm@1000f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1000f000 0x0 0x1000>;
- pdp0_mbox: mailbox@17610000 {
- compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
- reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- };
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
- timer@17810000 {
- compatible = "arm,armv7-timer-mem";
- reg = <0x0 0x17810000 0x0 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x0 0x20000000>;
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
- frame@17811000 {
- reg = <0x0 0x17811000 0x1000>,
- <0x0 0x17812000 0x1000>;
+ out-ports {
+ port {
+ spdm_tpdm_out: endpoint {
+ remote-endpoint = <&qdss_tpda_in1>;
+ };
+ };
+ };
+ };
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ funnel@10041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10041000 0x0 0x1000>;
- frame-number = <0>;
- };
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
- frame@17813000 {
- reg = <0x0 0x17813000 0x1000>;
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ port@0 {
+ reg = <0>;
- frame-number = <1>;
+ funnel0_in0: endpoint {
+ remote-endpoint = <&tn_ag_out>;
+ };
+ };
- status = "disabled";
- };
+ port@6 {
+ reg = <6>;
- frame@17815000 {
- reg = <0x0 0x17815000 0x1000>;
+ funnel0_in6: endpoint {
+ remote-endpoint = <&qdss_tpda_out>;
+ };
+ };
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ port@7 {
+ reg = <7>;
- frame-number = <2>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
- status = "disabled";
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint = <&aoss_funnel_in6>;
+ };
+ };
};
+ };
- frame@17817000 {
- reg = <0x0 0x17817000 0x1000>;
+ tpdm@1102c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1102c000 0x0 0x1000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
- frame-number = <3>;
+ qcom,dsb-msrs-num = <32>;
- status = "disabled";
+ out-ports {
+ port {
+ gcc_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in36>;
+ };
+ };
};
+ };
- frame@17819000 {
- reg = <0x0 0x17819000 0x1000>;
+ tpdm@11180000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11180000 0x0 0x1000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
- frame-number = <4>;
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
- status = "disabled";
+ out-ports {
+ port {
+ cdsp_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in0>;
+ };
+ };
};
+ };
- frame@1781b000 {
- reg = <0x0 0x1781b000 0x1000>;
+ tpdm@11185000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11185000 0x0 0x1000>;
- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
- frame-number = <5>;
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
- status = "disabled";
+ out-ports {
+ port {
+ cdsp_dpm1_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in5>;
+ };
+ };
};
+ };
- frame@1781d000 {
- reg = <0x0 0x1781d000 0x1000>;
+ tpdm@11186000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11186000 0x0 0x1000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
- frame-number = <6>;
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
- status = "disabled";
+ out-ports {
+ port {
+ cdsp_dpm2_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in6>;
+ };
+ };
};
};
- apps_rsc: rsc@18900000 {
- compatible = "qcom,rpmh-rsc";
- label = "apps_rsc";
- reg = <0x0 0x18900000 0x0 0x10000>,
- <0x0 0x18910000 0x0 0x10000>,
+ tpda@11188000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x11188000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ cdsp_tpda_in0: endpoint {
+ remote-endpoint = <&cdsp_tpdm_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ cdsp_tpda_in1: endpoint {
+ remote-endpoint = <&cdsp_llm_tpdm_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ cdsp_tpda_in2: endpoint {
+ remote-endpoint = <&cdsp_llm2_tpdm_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ cdsp_tpda_in3: endpoint {
+ remote-endpoint = <&cdsp_cmsr_tpdm_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ cdsp_tpda_in4: endpoint {
+ remote-endpoint = <&cdsp_cmsr2_tpdm_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ cdsp_tpda_in5: endpoint {
+ remote-endpoint = <&cdsp_dpm1_tpdm_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ cdsp_tpda_in6: endpoint {
+ remote-endpoint = <&cdsp_dpm2_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ cdsp_tpda_out: endpoint {
+ remote-endpoint = <&cdsp_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@11189000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x11189000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ cdsp_funnel_in0: endpoint {
+ remote-endpoint = <&cdsp_tpda_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ cdsp_funnel_out: endpoint {
+ remote-endpoint = <&tn_ag_in53>;
+ };
+ };
+ };
+ };
+
+ cti@11193000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x11193000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_wpss: cti@111ab000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x111ab000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ tpdm@111d0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x111d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ qm_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in35>;
+ };
+ };
+ };
+ };
+
+ itnoc@11200000 {
+ compatible = "qcom,coresight-itnoc";
+ reg = <0x0 0x11200000 0x0 0x3c00>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+
+ tn_ag_in6: endpoint {
+ remote-endpoint = <&mm_dsb_tpdm_out>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ tn_ag_in16: endpoint {
+ remote-endpoint = <&east_dsb_tpdm_out>;
+ };
+ };
+
+ port@21 {
+ reg = <0x21>;
+
+ tn_ag_in33: endpoint {
+ remote-endpoint = <&west_dsb_tpdm_out>;
+ };
+ };
+
+ port@23 {
+ reg = <0x23>;
+
+ tn_ag_in35: endpoint {
+ remote-endpoint = <&qm_tpdm_out>;
+ };
+ };
+
+ port@24 {
+ reg = <0x24>;
+
+ tn_ag_in36: endpoint {
+ remote-endpoint = <&gcc_tpdm_out>;
+ };
+ };
+
+ port@32 {
+ reg = <0x32>;
+
+ tn_ag_in50: endpoint {
+ remote-endpoint = <&pcie_rscc_tpda_out>;
+ };
+ };
+
+ port@35 {
+ reg = <0x35>;
+
+ tn_ag_in53: endpoint {
+ remote-endpoint = <&cdsp_funnel_out>;
+ };
+ };
+
+ port@3f {
+ reg = <0x3f>;
+
+ tn_ag_in63: endpoint {
+ remote-endpoint = <¢er_dsb_tpdm_out>;
+ };
+ };
+
+ port@40 {
+ reg = <0x40>;
+
+ tn_ag_in64: endpoint {
+ remote-endpoint = <&ipcc_cmb_tpdm_out>;
+ };
+ };
+
+ port@41 {
+ reg = <0x41>;
+
+ tn_ag_in65: endpoint {
+ remote-endpoint = <&qrng_tpdm_out>;
+ };
+ };
+
+ port@42 {
+ reg = <0x42>;
+
+ tn_ag_in66: endpoint {
+ remote-endpoint = <&pmu_tpdm_out>;
+ };
+ };
+
+ port@43 {
+ reg = <0x43>;
+
+ tn_ag_in67: endpoint {
+ remote-endpoint = <&rdpm_west_cmb0_tpdm_out>;
+ };
+ };
+
+ port@44 {
+ reg = <0x44>;
+
+ tn_ag_in68: endpoint {
+ remote-endpoint = <&rdpm_west_cmb1_tpdm_out>;
+ };
+ };
+
+ port@45 {
+ reg = <0x45>;
+
+ tn_ag_in69: endpoint {
+ remote-endpoint = <&rdpm_west_cmb2_tpdm_out>;
+ };
+ };
+
+ port@4b {
+ reg = <0x4b>;
+
+ tn_ag_in75: endpoint {
+ remote-endpoint = <&south_dsb2_tpdm_out>;
+ };
+ };
+
+ port@52 {
+ reg = <0x52>;
+
+ tn_ag_in82: endpoint {
+ remote-endpoint = <&south_dsb_tpdm_out>;
+ };
+ };
+
+ port@53 {
+ reg = <0x53>;
+
+ tn_ag_in83: endpoint {
+ remote-endpoint = <¢er_dsb1_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tn_ag_out: endpoint {
+ remote-endpoint = <&funnel0_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@11207000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11207000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ mm_dsb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@1120b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1120b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ east_dsb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in16>;
+ };
+ };
+ };
+ };
+
+ tpdm@11213000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11213000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ west_dsb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in33>;
+ };
+ };
+ };
+ };
+
+ tpdm@11219000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11219000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ center_dsb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in63>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ ipcc_cmb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in64>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ qrng_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in65>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ pmu_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in66>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ rdpm_west_cmb0_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in67>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121e000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ rdpm_west_cmb1_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in68>;
+ };
+ };
+ };
+ };
+
+ tpdm@1121f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1121f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ rdpm_west_cmb2_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in69>;
+ };
+ };
+ };
+ };
+
+ tpdm@11220000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11220000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ center_dsb1_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in83>;
+ };
+ };
+ };
+ };
+
+ tpdm@11224000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11224000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ south_dsb2_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in75>;
+ };
+ };
+ };
+ };
+
+ tpdm@11228000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11228000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ south_dsb_tpdm_out: endpoint {
+ remote-endpoint = <&tn_ag_in82>;
+ };
+ };
+ };
+ };
+
+ tpdm@11470000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11470000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ pcie_rscc_tpdm_out: endpoint {
+ remote-endpoint = <&pcie_rscc_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@11471000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x11471000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ pcie_rscc_tpda_in0: endpoint {
+ remote-endpoint = <&pcie_rscc_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ pcie_rscc_tpda_out: endpoint {
+ remote-endpoint = <&tn_ag_in50>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c03000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c03000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio4_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in4>;
+ };
+ };
+ };
+ };
+
+ funnel@11c04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x11c04000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@5 {
+ reg = <5>;
+
+ aoss_funnel_in5: endpoint {
+ remote-endpoint = <&aoss_tpda_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ aoss_funnel_in6: endpoint {
+ remote-endpoint = <&funnel0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ aoss_funnel_out: endpoint {
+ remote-endpoint = <&etf0_in>;
+ };
+ };
+ };
+ };
+
+ tmc_etf: tmc@11c05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x11c05000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etf0_in: endpoint {
+ remote-endpoint = <&aoss_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf0_out: endpoint {
+ remote-endpoint = <&swao_rep_in>;
+ };
+ };
+ };
+ };
+
+ replicator@11c06000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x11c06000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ swao_rep_in: endpoint {
+ remote-endpoint = <&etf0_out>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ swao_rep_out1: endpoint {
+ remote-endpoint = <&eud_in>;
+ };
+ };
+ };
+ };
+
+ tpda@11c08000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x11c08000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ aoss_tpda_in0: endpoint {
+ remote-endpoint = <&swao_prio0_tpdm_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ aoss_tpda_in1: endpoint {
+ remote-endpoint = <&swao_prio1_tpdm_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ aoss_tpda_in2: endpoint {
+ remote-endpoint = <&swao_prio2_tpdm_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ aoss_tpda_in3: endpoint {
+ remote-endpoint = <&swao_prio3_tpdm_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ aoss_tpda_in4: endpoint {
+ remote-endpoint = <&swao_prio4_tpdm_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ aoss_tpda_in5: endpoint {
+ remote-endpoint = <&swao_tpdm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ aoss_tpda_out: endpoint {
+ remote-endpoint = <&aoss_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c09000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio0_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c0a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c0a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio1_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c0b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c0b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio2_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c0c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c0c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_prio3_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@11c0d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x11c0d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ swao_tpdm_out: endpoint {
+ remote-endpoint = <&aoss_tpda_in5>;
+ };
+ };
+ };
+ };
+
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,glymur-smmu-500",
+ "qcom,smmu-500",
+ "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
+
+ dma-coherent;
+ };
+
+ pcie_smmu: iommu@15480000 {
+ compatible = "arm,smmu-v3";
+ reg = <0x0 0x15480000 0x0 0x20000>;
+ interrupts = <GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 962 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eventq", "cmdq-sync", "gerror";
+ dma-coherent;
+ #iommu-cells = <1>;
+ };
+
+ intc: interrupt-controller@17000000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x17000000 0x0 0x10000>,
+ <0x0 0x17080000 0x0 0x480000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <3>;
+ interrupt-controller;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic_its: msi-controller@17040000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x0 0x17040000 0x0 0x40000>;
+
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ watchdog@17600000 {
+ compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt";
+ reg = <0x0 0x17600000 0x0 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pdp0_mbox: mailbox@17610000 {
+ compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
+ reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ };
+
+ timer@17810000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x17810000 0x0 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x0 0x20000000>;
+
+ frame@17811000 {
+ reg = <0x0 0x17811000 0x1000>,
+ <0x0 0x17812000 0x1000>;
+
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <0>;
+ };
+
+ frame@17813000 {
+ reg = <0x0 0x17813000 0x1000>;
+
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <1>;
+
+ status = "disabled";
+ };
+
+ frame@17815000 {
+ reg = <0x0 0x17815000 0x1000>;
+
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <2>;
+
+ status = "disabled";
+ };
+
+ frame@17817000 {
+ reg = <0x0 0x17817000 0x1000>;
+
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <3>;
+
+ status = "disabled";
+ };
+
+ frame@17819000 {
+ reg = <0x0 0x17819000 0x1000>;
+
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <4>;
+
+ status = "disabled";
+ };
+
+ frame@1781b000 {
+ reg = <0x0 0x1781b000 0x1000>;
+
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <5>;
+
+ status = "disabled";
+ };
+
+ frame@1781d000 {
+ reg = <0x0 0x1781d000 0x1000>;
+
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+ frame-number = <6>;
+
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@18900000 {
+ compatible = "qcom,rpmh-rsc";
+ label = "apps_rsc";
+ reg = <0x0 0x18900000 0x0 0x10000>,
+ <0x0 0x18910000 0x0 0x10000>,
<0x0 0x18920000 0x0 0x10000>;
reg-names = "drv-0",
"drv-1",
};
};
};
+
+ tpdm-cdsp-llm {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ cdsp_llm_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm-cdsp-llm2 {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ cdsp_llm2_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm-cdsp-cmsr {
+ compatible = "qcom,coresight-static-tpdm";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,dsb-element-bits = <32>;
+
+ out-ports {
+ port {
+ cdsp_cmsr_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm-cdsp-cmsr2 {
+ compatible = "qcom,coresight-static-tpdm";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,dsb-element-bits = <32>;
+
+ out-ports {
+ port {
+ cdsp_cmsr2_tpdm_out: endpoint {
+ remote-endpoint = <&cdsp_tpda_in4>;
+ };
+ };
+ };
+ };
};
projects / thirdparty / kernel / linux.git / commitdiff
