#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
+#include <errno.h>
#include <fdt_support.h>
#include <init.h>
#include "../common/tdx-cfg-block.h"
+/*
+ * The address wrap-around is not linear: address bits above the module
+ * capacity alias back to the base with some low address bits XORed, as
+ * measured on 4GB and 8GB modules (bit 32 -> XOR 0xc000, bit 33 -> XOR
+ * 0x2000).
+ */
+static const struct ram_alias_check ram_alias_checks[] = {
+ { (void *)((uintptr_t)PHYS_SDRAM + SZ_4G), (void *)((uintptr_t)PHYS_SDRAM + 0xc000), SZ_8G },
+ { (void *)((uintptr_t)PHYS_SDRAM + SZ_2G), (void *)(PHYS_SDRAM), SZ_4G },
+ { NULL }
+};
+
int board_phys_sdram_size(phys_size_t *size)
{
- *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE;
+ phys_size_t sz;
+
+ sz = probe_ram_size_by_alias(ram_alias_checks);
+ if (!sz) {
+ puts("## WARNING: Less than 4GB RAM detected\n");
+ return -EINVAL;
+ }
+
+ *size = sz - PHYS_SDRAM_FW_RSVD;
return 0;
}
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
-/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above */
+/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above.
+ * Actual size is determined at runtime.
+ */
#define SZ_6G _AC(0x180000000, ULL)
-/* first 256MB reserved for firmware */
-#define CFG_SYS_INIT_RAM_ADDR 0x90000000
+/* The first 256MB of SDRAM is reserved for firmware (Cortex M7) */
+#define PHYS_SDRAM_FW_RSVD SZ_256M
+#define CFG_SYS_INIT_RAM_ADDR PHYS_SDRAM
#define CFG_SYS_INIT_RAM_SIZE SZ_2M
-#define CFG_SYS_SDRAM_BASE 0x90000000
-#define PHYS_SDRAM 0x90000000
-#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M)
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
+#define PHYS_SDRAM (0x80000000 + PHYS_SDRAM_FW_RSVD)
+#define PHYS_SDRAM_SIZE (SZ_2G - PHYS_SDRAM_FW_RSVD)
#define PHYS_SDRAM_2_SIZE SZ_6G
#endif