drm: renesas: rz-du: Add support for RZ/V2H(P) SoC

The LCD controller (LCDC) on the RZ/V2H(P) SoC is composed of Frame
Compression Processor (FCPVD), Video Signal Processor (VSPD), and
Display Unit (DU).

There is one LCDC unit available on the RZ/V2H(P) SoC which is connected
to the DSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250512182330.238259-3-prabhakar.mahadev-lad.rj@bp.renesas.com

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
index 5e40f0c1e7b083f49961d9eeaf0b9b9b0b4e5d8c..e1aa6a719529de7247318625fc58598e0219ee31 100644 (file)
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
@@ -50,9 +50,20 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
        }
 };
 
+static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {
+       .channels_mask = BIT(0),
+       .routes = {
+               [RZG2L_DU_OUTPUT_DSI0] = {
+                       .possible_outputs = BIT(0),
+                       .port = 0,
+               },
+       },
+};
+
 static const struct of_device_id rzg2l_du_of_table[] = {
        { .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info },
        { .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info },
+       { .compatible = "renesas,r9a09g057-du", .data = &rzg2l_du_r9a09g057_info },
        { /* sentinel */ }
 };