phy: freescale: imx8m-pcie: fix pcie link-up instability

[ Upstream commit 3a161017f1de55cc48be81f6156004c151f32677 ]

Leaving AUX_PLL_REFCLK_SEL at its reset default of AUX_IN (PLL clock)
proves to be more stable on the i.MX 8M Mini.

Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Link: https://lore.kernel.org/r/20240322130646.1016630-2-marcel@ziswiler.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index b700f52b7b6799f92c1c66f8c737efaae7a47dfc..11fcb1867118c3662c9a9b7f6c103dca5af4c768 100644 (file)
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -110,8 +110,10 @@ static int imx8_pcie_phy_power_on(struct phy *phy)
                /* Source clock from SoC internal PLL */
                writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
                       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
-               writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
-                      imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
+               if (imx8_phy->drvdata->variant != IMX8MM) {
+                       writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
+                              imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
+               }
                val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;
                writel(val | ANA_AUX_RX_TERM_GND_EN,
                       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);