drm/i915/dp: Fail state computation for invalid min/max link BPP values

Make sure that state computation fails if the minimum/maximum link BPP
values got invalid as a result of limiting both of these values
separately to the corresponding source/sink capability limits.

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251215192357.172201-14-imre.deak@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 57fcde656108c5fc6839541a23fbd7f9ef4cc829..a89c9eec62b3307ec96ebdb309cdb96909f4791a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2646,7 +2646,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
        limits->link.max_bpp_x16 = max_link_bpp_x16;
 
        drm_dbg_kms(display->drm,
-                   "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
+                   "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d min link_bpp " FXP_Q4_FMT " max link_bpp " FXP_Q4_FMT "\n",
                    encoder->base.base.id, encoder->base.name,
                    crtc->base.base.id, crtc->base.name,
                    adjusted_mode->crtc_clock,
@@ -2654,8 +2654,13 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
                    limits->max_lane_count,
                    limits->max_rate,
                    limits->pipe.max_bpp,
+                   FXP_Q4_ARGS(limits->link.min_bpp_x16),
                    FXP_Q4_ARGS(limits->link.max_bpp_x16));
 
+       if (limits->link.min_bpp_x16 <= 0 ||
+           limits->link.min_bpp_x16 > limits->link.max_bpp_x16)
+               return false;
+
        return true;
 }