/* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
partition@2800000 {
label = "ubia";
- reg = <0x2800000 0x6C00000>;
+ reg = <0x2800000 0x6c00000>;
};
/* ubib (second OpenWrt) */
partition@9400000 {
label = "ubib";
- reg = <0x9400000 0x6C00000>;
+ reg = <0x9400000 0x6c00000>;
};
};
};
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
#iommu-cells = <1>;
- stream-match-mask = <0x7C00>;
+ stream-match-mask = <0x7c00>;
dma-coherent;
#global-interrupts = <12>;
// global secure fault
reg = <0 0x5000000 0 0x800000>;
#global-interrupts = <12>;
#iommu-cells = <1>;
- stream-match-mask = <0x7C00>;
+ stream-match-mask = <0x7c00>;
dma-coherent;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* global secure fault */
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* combined secure interrupt */
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster0_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster1_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster2_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster3_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster4_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster5_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster6_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <128>;
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <192>;
next-level-cache = <&cluster7_l2>;
};
pinctrl_i2c2: i2c2grp {
- fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001C4>,
- <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001C4>;
+ fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c4>,
+ <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c4>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
- fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001C4>,
- <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001C4>;
+ fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c4>,
+ <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c4>;
};
pinctrl_i2c3: i2c3grp {
- fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001C4>,
- <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001C4>;
+ fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c4>,
+ <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c4>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
- fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001C4>,
- <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001C4>;
+ fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c4>,
+ <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c4>;
};
pinctrl_pwm3: pwm3grp {
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
- MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1C0
+ MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x1c0
>;
};
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
- MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0
+ MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c0
>;
};
};
pinctrl_mcu_int: mcuintgrp {
- fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1C0>; /* MCU_INT# */
+ fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x1c0>; /* MCU_INT# */
};
/* SMARC LCD1_BKLT_PWM */
/* SMARC SLEEP# */
pinctrl_sleep: sleepgrp {
- fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1C0>; /* SMARC S149 - SLEEP# */
+ fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1c0>; /* SMARC S149 - SLEEP# */
};
/* SMARC SMB_ALERT# */
pinctrl_smb_alert: smbalertgrp {
- fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1C0>; /* SMARC P1 - SMB_ALERT# */
+ fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x1c0>; /* SMARC P1 - SMB_ALERT# */
};
/* TPM_CS# */
compatible = "shared-dma-pool";
reusable;
size = <0 0x38000000>;
- alloc-ranges = <0 0x40000000 0 0xB0000000>;
+ alloc-ranges = <0 0x40000000 0 0xb0000000>;
linux,cma-default;
};
};
compatible = "shared-dma-pool";
reusable;
size = <0 0x38000000>;
- alloc-ranges = <0 0x40000000 0 0xB0000000>;
+ alloc-ranges = <0 0x40000000 0 0xb0000000>;
linux,cma-default;
};
};
pinctrl_hpdet: hpdetgrp {
fsl,pins = <
- MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xC0 /* HP_DET */
+ MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0xc0 /* HP_DET */
>;
};
pinctrl_keys: keysgrp {
fsl,pins = <
/* VOL- */
- MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01C0
+ MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17 0x01c0
/* VOL+ */
- MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01C0
+ MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16 0x01c0
>;
};
pinctrl_tcpc: tcpcgrp {
fsl,pins = <
/* TCPC_INT */
- MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01C0
+ MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x01c0
>;
};
pinctrl_mipi_csi0: mipi-csi0grp {
fsl,pins = <
- IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041
- IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041
- IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041
+ IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xc0000041
+ IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xc0000041
+ IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041
>;
};
pinctrl_mipi_csi1: mipi-csi1grp {
fsl,pins = <
- IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041
- IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041
- IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041
+ IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xc0000041
+ IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xc0000041
+ IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xc0000041
>;
};
reg = <0x0 0x100>;
clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
enable-method = "psci";
- i-cache-size = <0xC000>;
+ i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
- <0x0 0x51b00000 0 0xC0000>, /* GICR */
+ <0x0 0x51b00000 0 0xc0000>, /* GICR */
<0x0 0x52000000 0 0x2000>, /* GICC */
<0x0 0x52010000 0 0x1000>, /* GICH */
<0x0 0x52020000 0 0x20000>; /* GICV */
pinctrl_mipi_csi0: mipi-csi0grp {
fsl,pins = <
- IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041
- IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041
- IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041
+ IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xc0000041
+ IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xc0000041
+ IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xc0000041
>;
};
};
pinctrl_csi_mclk: csimclkgrp {
- fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041>; /* SODIMM 75 / X3-12 */
+ fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xc0000041>; /* SODIMM 75 / X3-12 */
};
pinctrl_ext_io0: extio0grp {
linux_cma: linux,cma {
compatible = "shared-dma-pool";
- alloc-ranges = <0 0x80000000 0 0x7F000000>;
+ alloc-ranges = <0 0x80000000 0 0x7f000000>;
reusable;
size = <0 0x3c000000>;
linux,cma-default;
compatible = "shared-dma-pool";
reusable;
size = <0 0x3c000000>;
- alloc-ranges = <0 0x80000000 0 0x7F000000>;
+ alloc-ranges = <0 0x80000000 0 0x7f000000>;
linux,cma-default;
};
};
status = "disabled";
};
- swt7: watchdog@4020C000 {
+ swt7: watchdog@4020c000 {
compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
- reg = <0x4020C000 0x1000>;
+ reg = <0x4020c000 0x1000>;
clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
clock-names = "counter", "module", "register";
status = "disabled";
};
dspi1-grp3 {
- pinmux = <0x5F0>;
+ pinmux = <0x5f0>;
input-enable;
slew-rate = <150>;
bias-pull-up;
};
dspi1-grp4 {
- pinmux = <0x3D92>,
- <0x3DA2>,
- <0x3DB2>;
+ pinmux = <0x3d92>,
+ <0x3da2>,
+ <0x3db2>;
};
};
};
dspi5-grp1 {
- pinmux = <0xA0>;
+ pinmux = <0xa0>;
input-enable;
slew-rate = <150>;
bias-pull-up;
};
dspi5-grp2 {
- pinmux = <0x3ED2>,
- <0x3EE2>,
- <0x3EF2>;
+ pinmux = <0x3ed2>,
+ <0x3ee2>,
+ <0x3ef2>;
};
dspi5-grp3 {
- pinmux = <0xB3>;
+ pinmux = <0xb3>;
output-enable;
slew-rate = <150>;
};
dspi5-grp4 {
- pinmux = <0xC3>;
+ pinmux = <0xc3>;
output-enable;
input-enable;
slew-rate = <150>;
};
dspi1-grp3 {
- pinmux = <0x5F0>;
+ pinmux = <0x5f0>;
input-enable;
slew-rate = <150>;
bias-pull-up;
};
dspi1-grp4 {
- pinmux = <0x3D92>,
- <0x3DA2>,
- <0x3DB2>;
+ pinmux = <0x3d92>,
+ <0x3da2>,
+ <0x3db2>;
};
};
};
dspi5-grp1 {
- pinmux = <0xA0>;
+ pinmux = <0xa0>;
input-enable;
slew-rate = <150>;
bias-pull-up;
};
dspi5-grp2 {
- pinmux = <0x3ED2>,
- <0x3EE2>,
- <0x3EF2>;
+ pinmux = <0x3ed2>,
+ <0x3ee2>,
+ <0x3ef2>;
};
dspi5-grp3 {
- pinmux = <0xB3>;
+ pinmux = <0xb3>;
output-enable;
slew-rate = <150>;
};
dspi5-grp4 {
- pinmux = <0xC3>;
+ pinmux = <0xc3>;
output-enable;
input-enable;
slew-rate = <150>;