]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: freescale: Use lowercase hex
authorKrzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Tue, 23 Dec 2025 15:26:27 +0000 (16:26 +0100)
committerShawn Guo <shawnguo@kernel.org>
Tue, 30 Dec 2025 13:11:53 +0000 (21:11 +0800)
The DTS code coding style expects lowercase hex for values and unit
addresses.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
21 files changed:
arch/arm64/boot/dts/freescale/fsl-ls1088a-ten64.dts
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts
arch/arm64/boot/dts/freescale/imx8mp-libra-rdk-fpsc.dts
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
arch/arm64/boot/dts/freescale/imx8mp-toradex-smarc.dtsi
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
arch/arm64/boot/dts/freescale/imx8qm.dtsi
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
arch/arm64/boot/dts/freescale/s32g3.dtsi
arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi

index 71765ec91745ec3f340dfd4d1c658d1e8241aebc..f51508952d51cbec5ccc85cb92a8d6534c039834 100644 (file)
                        /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */
                        partition@2800000 {
                                label = "ubia";
-                               reg = <0x2800000 0x6C00000>;
+                               reg = <0x2800000 0x6c00000>;
                        };
 
                        /* ubib (second OpenWrt) */
                        partition@9400000 {
                                label = "ubib";
-                               reg = <0x9400000 0x6C00000>;
+                               reg = <0x9400000 0x6c00000>;
                        };
                };
        };
index b2f6cd237be046123de9342e2167aa32248a8a16..99016768b73f210a6d086e9f7eac6f3629614272 100644 (file)
                        compatible = "arm,mmu-500";
                        reg = <0 0x5000000 0 0x800000>;
                        #iommu-cells = <1>;
-                       stream-match-mask = <0x7C00>;
+                       stream-match-mask = <0x7c00>;
                        dma-coherent;
                        #global-interrupts = <12>;
                                     // global secure fault
index 9421fdd7e30e3524225220f215420097a0d5f67a..6073e426774aad30a7a325fa0f562c0c14068ab9 100644 (file)
                        reg = <0 0x5000000 0 0x800000>;
                        #global-interrupts = <12>;
                        #iommu-cells = <1>;
-                       stream-match-mask = <0x7C00>;
+                       stream-match-mask = <0x7c00>;
                        dma-coherent;
                        interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* global secure fault */
                                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* combined secure interrupt */
index d899c0355e51dd457a4e7259709cea98a488f557..853b01452813a7826a5029f7196d0d4c03f5319a 100644 (file)
@@ -35,7 +35,7 @@
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster0_l2>;
@@ -52,7 +52,7 @@
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster0_l2>;
@@ -69,7 +69,7 @@
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster1_l2>;
@@ -86,7 +86,7 @@
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster1_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster2_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster2_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster3_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster3_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster4_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster4_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster5_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster5_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster6_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster6_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster7_l2>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
                        d-cache-sets = <128>;
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <192>;
                        next-level-cache = <&cluster7_l2>;
index 0d009f4be804e860e2b333dd7baa94eb0627fa37..664f4a6950a82af8ac38288bb0d71517eda91580 100644 (file)
        };
 
        pinctrl_i2c2: i2c2grp {
-               fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL              0x400001C4>,
-                          <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA              0x400001C4>;
+               fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL              0x400001c4>,
+                          <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA              0x400001c4>;
        };
 
        pinctrl_i2c2_gpio: i2c2gpiogrp {
-               fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16            0x400001C4>,
-                          <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17            0x400001C4>;
+               fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16            0x400001c4>,
+                          <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17            0x400001c4>;
        };
 
        pinctrl_i2c3: i2c3grp {
-               fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL              0x400001C4>,
-                          <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA              0x400001C4>;
+               fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL              0x400001c4>,
+                          <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA              0x400001c4>;
        };
 
        pinctrl_i2c3_gpio: i2c3gpiogrp {
-               fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18            0x400001C4>,
-                          <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19            0x400001C4>;
+               fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18            0x400001c4>,
+                          <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19            0x400001c4>;
        };
 
        pinctrl_pwm3: pwm3grp {
index ec1f1002224858a154d77c0d80225ef26cb6465c..86b8c5af4153d15e6b61c0d4b3bc5026a290d9aa 100644 (file)
        };
        pinctrl_rtc: rtcgrp {
                fsl,pins = <
-                       MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25      0x1C0
+                       MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25      0x1c0
                >;
        };
 };
index 90ec73068a6deb71554b62be951f3010a4e8c5c5..0fe52c73fc8fa5ac5bb52eb2b532323fe511f52e 100644 (file)
 
        pinctrl_rtc: rtcgrp {
                fsl,pins = <
-                       MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19      0x1C0
+                       MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19      0x1c0
                >;
        };
 
index bebe19eb360f88926d59843169c15a21eb50e11a..0348da385f23992e50eec5cd1bf84d566440ca60 100644 (file)
        };
 
        pinctrl_mcu_int: mcuintgrp {
-               fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08        0x1C0>; /* MCU_INT# */
+               fsl,pins = <MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08        0x1c0>; /* MCU_INT# */
        };
 
        /* SMARC LCD1_BKLT_PWM */
 
        /* SMARC SLEEP# */
        pinctrl_sleep: sleepgrp {
-               fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1C0>; /* SMARC S149 - SLEEP# */
+               fsl,pins = <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1c0>; /* SMARC S149 - SLEEP# */
        };
 
        /* SMARC SMB_ALERT# */
        pinctrl_smb_alert: smbalertgrp {
-               fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16       0x1C0>; /* SMARC P1 - SMB_ALERT# */
+               fsl,pins = <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16       0x1c0>; /* SMARC P1 - SMB_ALERT# */
        };
 
        /* TPM_CS# */
index 6e927ff1e967a9036be52f6e31b381d5bdac3984..b7f69c92b7748fa67c94a120b17ac6783470a36f 100644 (file)
                        compatible = "shared-dma-pool";
                        reusable;
                        size = <0 0x38000000>;
-                       alloc-ranges = <0 0x40000000 0 0xB0000000>;
+                       alloc-ranges = <0 0x40000000 0 0xb0000000>;
                        linux,cma-default;
                };
        };
index fdfe246c5640741c1eb634b7018fcfa377c8300d..ad49bf85a04d39e32322c13c2b6ef57e82f79d40 100644 (file)
                        compatible = "shared-dma-pool";
                        reusable;
                        size = <0 0x38000000>;
-                       alloc-ranges = <0 0x40000000 0 0xB0000000>;
+                       alloc-ranges = <0 0x40000000 0 0xb0000000>;
                        linux,cma-default;
                };
        };
index d9f203c795197a8d02e6bfa831df6eacdefdc4b3..aadaeef928bd978b4790c46ebaf276377a01e191 100644 (file)
 
        pinctrl_hpdet: hpdetgrp {
                fsl,pins = <
-                       MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20        0xC0   /* HP_DET */
+                       MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20        0xc0   /* HP_DET */
                >;
        };
 
index 9e0e2d7271efbe0c9f2713ad9a05a6d0d7db5edc..2975e9451661705c9d4df1e0d0b617a44a271915 100644 (file)
        pinctrl_keys: keysgrp {
                fsl,pins = <
                        /* VOL- */
-                       MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17       0x01C0
+                       MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17       0x01c0
                        /* VOL+ */
-                       MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16        0x01C0
+                       MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16        0x01c0
                >;
        };
 
        pinctrl_tcpc: tcpcgrp {
                fsl,pins = <
                        /* TCPC_INT */
-                       MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x01C0
+                       MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10      0x01c0
                >;
        };
 
index 779d9f78fb8196b04c41516963f16ece082360e3..7d4574c6de1d6ffc87edff24459fb2aea3a0283b 100644 (file)
 
        pinctrl_mipi_csi0: mipi-csi0grp {
                fsl,pins = <
-                       IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27               0xC0000041
-                       IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28               0xC0000041
-                       IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT        0xC0000041
+                       IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27               0xc0000041
+                       IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28               0xc0000041
+                       IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT        0xc0000041
                >;
        };
 
        pinctrl_mipi_csi1: mipi-csi1grp {
                fsl,pins = <
-                       IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30               0xC0000041
-                       IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31               0xC0000041
-                       IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT        0xC0000041
+                       IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30               0xc0000041
+                       IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31               0xc0000041
+                       IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT        0xc0000041
                >;
        };
 
index 9e7309a0ca51fba66257065f98bef77acddcf930..f7e28f22343a73a1e9e16f1fe77657946ff8933c 100644 (file)
                        reg = <0x0 0x100>;
                        clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>;
                        enable-method = "psci";
-                       i-cache-size = <0xC000>;
+                       i-cache-size = <0xc000>;
                        i-cache-line-size = <64>;
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
        gic: interrupt-controller@51a00000 {
                compatible = "arm,gic-v3";
                reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
-                     <0x0 0x51b00000 0 0xC0000>, /* GICR */
+                     <0x0 0x51b00000 0 0xc0000>, /* GICR */
                      <0x0 0x52000000 0 0x2000>,  /* GICC */
                      <0x0 0x52010000 0 0x1000>,  /* GICH */
                      <0x0 0x52020000 0 0x20000>; /* GICV */
index 50a97c0297c72deef6aecf0475a796e739867a50..40a0bc9f4e8485ba5c9d57245a8ea2e0a625d602 100644 (file)
 
        pinctrl_mipi_csi0: mipi-csi0grp {
                fsl,pins = <
-                       IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07              0xC0000041
-                       IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08              0xC0000041
-                       IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT       0xC0000041
+                       IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07              0xc0000041
+                       IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08              0xc0000041
+                       IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT       0xc0000041
                >;
        };
 
index 8e9e841cc82813f11e41616d53e7dc8f77f86b68..014808774b0e94b800f6158770aa21d953870ac7 100644 (file)
        };
 
        pinctrl_csi_mclk: csimclkgrp {
-               fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK                         0xC0000041>;    /* SODIMM  75 / X3-12 */
+               fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK                         0xc0000041>;    /* SODIMM  75 / X3-12 */
        };
 
        pinctrl_ext_io0: extio0grp {
index 3081513cfc045545153585941062b1e0653ad6db..d4184fb8b28cd8bf1996f777bd8c08f5dccb742c 100644 (file)
 
                linux_cma: linux,cma {
                        compatible = "shared-dma-pool";
-                       alloc-ranges = <0 0x80000000 0 0x7F000000>;
+                       alloc-ranges = <0 0x80000000 0 0x7f000000>;
                        reusable;
                        size = <0 0x3c000000>;
                        linux,cma-default;
index afbdadcb368638b9003d9959aa8f1253bdd917a2..a0752f21edf924e3e5832404f84ea7405749e8a8 100644 (file)
                        compatible = "shared-dma-pool";
                        reusable;
                        size = <0 0x3c000000>;
-                       alloc-ranges = <0 0x80000000 0 0x7F000000>;
+                       alloc-ranges = <0 0x80000000 0 0x7f000000>;
                        linux,cma-default;
                };
        };
index eff7673e7f3412ddabf5acec6ae7c98756140242..e314f3c7d61d00d48dbea70bd36291882f2f0ef1 100644 (file)
                        status = "disabled";
                };
 
-               swt7: watchdog@4020C000 {
+               swt7: watchdog@4020c000 {
                        compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
-                       reg = <0x4020C000 0x1000>;
+                       reg = <0x4020c000 0x1000>;
                        clocks = <&clks 0x3a>, <&clks 0x3b>, <&clks 0x3b>;
                        clock-names = "counter", "module", "register";
                        status = "disabled";
index f1969cdcef19e33da3bf7a38bbc32892b5517eb1..803ff45310771326aeac15188ccf63bb4ea702ba 100644 (file)
                };
 
                dspi1-grp3 {
-                       pinmux = <0x5F0>;
+                       pinmux = <0x5f0>;
                        input-enable;
                        slew-rate = <150>;
                        bias-pull-up;
                };
 
                dspi1-grp4 {
-                       pinmux = <0x3D92>,
-                                <0x3DA2>,
-                                <0x3DB2>;
+                       pinmux = <0x3d92>,
+                                <0x3da2>,
+                                <0x3db2>;
                };
        };
 
                };
 
                dspi5-grp1 {
-                       pinmux = <0xA0>;
+                       pinmux = <0xa0>;
                        input-enable;
                        slew-rate = <150>;
                        bias-pull-up;
                };
 
                dspi5-grp2 {
-                       pinmux = <0x3ED2>,
-                                <0x3EE2>,
-                                <0x3EF2>;
+                       pinmux = <0x3ed2>,
+                                <0x3ee2>,
+                                <0x3ef2>;
                };
 
                dspi5-grp3 {
-                       pinmux = <0xB3>;
+                       pinmux = <0xb3>;
                        output-enable;
                        slew-rate = <150>;
                };
 
                dspi5-grp4 {
-                       pinmux = <0xC3>;
+                       pinmux = <0xc3>;
                        output-enable;
                        input-enable;
                        slew-rate = <150>;
index 3bc3335c92482adc111efca90ace0a95f48bd7be..979868f6d2c5cbf10f16088e180eae567c8aea54 100644 (file)
                };
 
                dspi1-grp3 {
-                       pinmux = <0x5F0>;
+                       pinmux = <0x5f0>;
                        input-enable;
                        slew-rate = <150>;
                        bias-pull-up;
                };
 
                dspi1-grp4 {
-                       pinmux = <0x3D92>,
-                                <0x3DA2>,
-                                <0x3DB2>;
+                       pinmux = <0x3d92>,
+                                <0x3da2>,
+                                <0x3db2>;
                };
        };
 
                };
 
                dspi5-grp1 {
-                       pinmux = <0xA0>;
+                       pinmux = <0xa0>;
                        input-enable;
                        slew-rate = <150>;
                        bias-pull-up;
                };
 
                dspi5-grp2 {
-                       pinmux = <0x3ED2>,
-                                <0x3EE2>,
-                                <0x3EF2>;
+                       pinmux = <0x3ed2>,
+                                <0x3ee2>,
+                                <0x3ef2>;
                };
 
                dspi5-grp3 {
-                       pinmux = <0xB3>;
+                       pinmux = <0xb3>;
                        output-enable;
                        slew-rate = <150>;
                };
 
                dspi5-grp4 {
-                       pinmux = <0xC3>;
+                       pinmux = <0xc3>;
                        output-enable;
                        input-enable;
                        slew-rate = <150>;