arm: mach-k3: am62ax: fix MCU_CLKOUT0 parent clock mux

Much like what was fixed on the AM62x and AM62Px platforms[0]. The
CU_CLKOUT0 has two (25mhz and 50mhz) mux options however the clock
structure incorrectly duplicated the first 50mhz option twice. Fix this
for the AM62A platforms so the 25mhz option is selectable.

[0] https://lore.kernel.org/all/20250408161211.3165588-1-parth105105@gmail.com/

Reported-by: Parth Pancholi <parth.pancholi@toradex.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>

diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c
index 7f1b6d5b4e0a745aa3a2d9e2ef112de1ae7633ca..9d9a43c055be76635cb735129452ab3a782636ea 100644 (file)
--- a/arch/arm/mach-k3/r5/am62ax/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c
@@ -64,7 +64,7 @@ static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
 
 static const char * const clkout0_ctrl_out0_parents[] = {
        "hsdiv4_16fft_main_2_hsdivout1_clk",
-       "hsdiv4_16fft_main_2_hsdivout1_clk",
+       "hsdiv4_16fft_main_2_hsdivout1_clk10",
 };
 
 static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
@@ -200,6 +200,7 @@ static const struct clk_data clk_list[] = {
        CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
+       CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
        CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
@@ -316,7 +317,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
        DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(157, 20, "clkout0_ctrl_out0"),
        DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
+       DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"),
        DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
        DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),