RISC-V: Add RISC-V into vect_cmdline_needed

Like all other targets, we add RISC-V into vect_cmdline_needed.

This patch fixes following FAILs:

FAIL: gcc.dg/tree-ssa/gen-vect-11b.c scan-tree-dump-times vect "vectorized 0 loops" 1
FAIL: gcc.dg/tree-ssa/gen-vect-11c.c scan-tree-dump-times vect "vectorized 0 loops" 1
FAIL: gcc.dg/tree-ssa/gen-vect-26.c scan-tree-dump-times vect "Alignment of access forced using peeling" 1
FAIL: gcc.dg/tree-ssa/gen-vect-28.c scan-tree-dump-times vect "Alignment of access forced using peeling" 1

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add RISC-V.

diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 6ef53e07a453f27a20bf0ce029fdd4cd4edc33a3..0317fc102ef729c1cbabae60311360150998517a 100644 (file)
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4036,7 +4036,8 @@ proc check_effective_target_vect_cmdline_needed { } {
             || ([istarget sparc*-*-*] && [check_effective_target_sparc_vis])
             || ([istarget arm*-*-*] && [check_effective_target_arm_neon])
             || [istarget aarch64*-*-*]
-             || [istarget amdgcn*-*-*]} {
+            || [istarget amdgcn*-*-*]
+            || [istarget riscv*-*-*]} {
            return 0
        } else {
            return 1