arm64: dts: imx8mm-var-som-symphony: Enable uSD on USDHC2

Enable the microSD slot on the VAR-SOM Symphony carrier board.

Configure USDHC2 with card-detect GPIO, pinctrl states for the supported
bus speeds and the required VMMC supply.

Update the VMMC regulator to match the latest carrier revision by moving
the enable GPIO to GPIO4_IO22 and adding the required off-on delay.

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
index a425ee0ed8a95be453e009e78f1c43a97b848446..6da29845985f6b0e94134f357fb7476d2cd81f83 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
@@ -24,7 +24,8 @@
                regulator-name = "VSD_3V3";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
-               gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+               gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+               off-on-delay-us = <20000>;
                enable-active-high;
        };
 
@@ -220,6 +221,18 @@
        status = "okay";
 };
 
+/* SD */
+&usdhc2 {
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
+       pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+       pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+       cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+       vmmc-supply = <&reg_usdhc2_vmmc>;
+       bus-width = <4>;
+       status = "okay";
+};
+
 &pinctrl_fec1 {
        fsl,pins = <
                MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
@@ -280,7 +293,7 @@
 
        pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
                fsl,pins = <
-                       MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
+                       MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22        0x41
                >;
        };
 
@@ -304,4 +317,46 @@
                        MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX     0x140
                >;
        };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
+                       MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
+                       MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
+                       MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
+                       MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
+                       MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
+                       MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10      0xc1
+               >;
+       };
 };