if ARCH_RENESAS
-# Renesas ARM SoCs R-Car Gen3/Gen4 (64bit)
+config TMU_TIMER
+ bool
+
+# Renesas ARM SoCs R-Car Gen3/Gen4/Gen5 (64bit Cortex-A / 32bit Cortex-M/R)
config RCAR_64
bool
- select ARM64
+ select CPU_V8M if RCAR_64_RSIP
+ select ARM64 if !RCAR_64_RSIP
select CMD_CACHE
- select OF_BOARD_SETUP
+ select OF_BOARD_SETUP if !RCAR_64_RSIP
select PHY
select PINCONF
select PINCTRL
- select POSITION_INDEPENDENT
+ select POSITION_INDEPENDENT if !RCAR_64_RSIP
imply CMD_FS_UUID
imply CMD_GPT
imply CMD_MMC_SWRITE if MMC
if RCAR_GEN5
+config RCAR_64_RSIP
+ bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)"
+ select SKIP_RELOCATE_CODE
+ select TMU_TIMER
+ help
+ Build U-Boot for the Cortex-M33 RSIP core present on selected SoC.
+ The default is n, meaning U-Boot is built for the Cortex-A core.
+
menu "Select Target SoC"
config R8A78000
source "board/renesas/ironhide/Kconfig"
+config SKIP_RELOCATE_CODE_DATA_OFFSET
+ default 0xa0000000 if RCAR_64_RSIP
+
endif
/*
* R-Car (R8A78000) I/O Addresses
*/
+#if defined(CONFIG_RCAR_64_RSIP)
+/* Cortex-M33 address */
+#define TMU_BASE 0xC0680000
+#else
+/* Cortex-A720AE address */
#define TMU_BASE 0x1C030000
+#endif
/* Arm Generic Timer */
#define CNTCR_BASE 0x1C000FFF /* Region 0 */
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
+/* Timer */
+#if defined(CONFIG_RCAR_64_RSIP)
+#define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
+#define CFG_SYS_TIMER_RATE (133333333 / 4)
+#endif
+
/* Environment setting */
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"