with flags update:
PPC float load insns
with one register + one 16 bits immediate args with flags update:
- lfs 0010000000000001, -120 => 37e0000000000000, 1001c0b0
- lfs 00100094e0000359, -112 => 37e0009400000000, 1001c0b0
- lfs 3fe0000000000001, -104 => 3ffc000000000000, 1001c0b0
- lfs 3fe00094e0000359, -96 => 3ffc001280000000, 1001c0b0
- lfs 8010000000000001, -88 => b7e0000000000000, 1001c0b0
- lfs 80100094e0000359, -80 => b7e0009400000000, 1001c0b0
- lfs bfe0000000000001, -72 => bffc000000000000, 1001c0b0
- lfs bfe00094e0000359, -64 => bffc001280000000, 1001c0b0
- lfs 0000000000000000, -56 => 0000000000000000, 1001c0b0
- lfs 8000000000000000, -48 => 8000000000000000, 1001c0b0
- lfs 7ff0000000000000, -40 => 7ffe000000000000, 1001c0b0
- lfs fff0000000000000, -32 => fffe000000000000, 1001c0b0
- lfs 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 1001c0b0
- lfs fff7ffffffffffff, -16 => fffeffffe0000000, 1001c0b0
- lfs 7ff8000000000000, -8 => 7fff000000000000, 1001c0b0
- lfs 0010000000000001, 0 => 37e0000000000000, 1001c038
- lfs 00100094e0000359, 8 => 37e0009400000000, 1001c038
- lfs 3fe0000000000001, 16 => 3ffc000000000000, 1001c038
- lfs 3fe00094e0000359, 24 => 3ffc001280000000, 1001c038
- lfs 8010000000000001, 32 => b7e0000000000000, 1001c038
- lfs 80100094e0000359, 40 => b7e0009400000000, 1001c038
- lfs bfe0000000000001, 48 => bffc000000000000, 1001c038
- lfs bfe00094e0000359, 56 => bffc001280000000, 1001c038
- lfs 0000000000000000, 64 => 0000000000000000, 1001c038
- lfs 8000000000000000, 72 => 8000000000000000, 1001c038
- lfs 7ff0000000000000, 80 => 7ffe000000000000, 1001c038
- lfs fff0000000000000, 88 => fffe000000000000, 1001c038
- lfs 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 1001c038
- lfs fff7ffffffffffff, 104 => fffeffffe0000000, 1001c038
- lfs 7ff8000000000000, 112 => 7fff000000000000, 1001c038
- lfs fff8000000000000, 120 => ffff000000000000, 1001c038
-
- lfsu 0010000000000001, -120 => 37e0000000000000, 1001c038
- lfsu 00100094e0000359, -112 => 37e0009400000000, 1001c040
- lfsu 3fe0000000000001, -104 => 3ffc000000000000, 1001c048
- lfsu 3fe00094e0000359, -96 => 3ffc001280000000, 1001c050
- lfsu 8010000000000001, -88 => b7e0000000000000, 1001c058
- lfsu 80100094e0000359, -80 => b7e0009400000000, 1001c060
- lfsu bfe0000000000001, -72 => bffc000000000000, 1001c068
- lfsu bfe00094e0000359, -64 => bffc001280000000, 1001c070
- lfsu 0000000000000000, -56 => 0000000000000000, 1001c078
- lfsu 8000000000000000, -48 => 8000000000000000, 1001c080
- lfsu 7ff0000000000000, -40 => 7ffe000000000000, 1001c088
- lfsu fff0000000000000, -32 => fffe000000000000, 1001c090
- lfsu 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 1001c098
- lfsu fff7ffffffffffff, -16 => fffeffffe0000000, 1001c0a0
- lfsu 7ff8000000000000, -8 => 7fff000000000000, 1001c0a8
- lfsu 0010000000000001, 0 => 37e0000000000000, 1001c038
- lfsu 00100094e0000359, 8 => 37e0009400000000, 1001c040
- lfsu 3fe0000000000001, 16 => 3ffc000000000000, 1001c048
- lfsu 3fe00094e0000359, 24 => 3ffc001280000000, 1001c050
- lfsu 8010000000000001, 32 => b7e0000000000000, 1001c058
- lfsu 80100094e0000359, 40 => b7e0009400000000, 1001c060
- lfsu bfe0000000000001, 48 => bffc000000000000, 1001c068
- lfsu bfe00094e0000359, 56 => bffc001280000000, 1001c070
- lfsu 0000000000000000, 64 => 0000000000000000, 1001c078
- lfsu 8000000000000000, 72 => 8000000000000000, 1001c080
- lfsu 7ff0000000000000, 80 => 7ffe000000000000, 1001c088
- lfsu fff0000000000000, 88 => fffe000000000000, 1001c090
- lfsu 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 1001c098
- lfsu fff7ffffffffffff, 104 => fffeffffe0000000, 1001c0a0
- lfsu 7ff8000000000000, 112 => 7fff000000000000, 1001c0a8
- lfsu fff8000000000000, 120 => ffff000000000000, 1001c0b0
-
- lfd 0010000000000001, -120 => 0010000000000001, 1001c0b0
- lfd 00100094e0000359, -112 => 00100094e0000359, 1001c0b0
- lfd 3fe0000000000001, -104 => 3fe0000000000001, 1001c0b0
- lfd 3fe00094e0000359, -96 => 3fe00094e0000359, 1001c0b0
- lfd 8010000000000001, -88 => 8010000000000001, 1001c0b0
- lfd 80100094e0000359, -80 => 80100094e0000359, 1001c0b0
- lfd bfe0000000000001, -72 => bfe0000000000001, 1001c0b0
- lfd bfe00094e0000359, -64 => bfe00094e0000359, 1001c0b0
- lfd 0000000000000000, -56 => 0000000000000000, 1001c0b0
- lfd 8000000000000000, -48 => 8000000000000000, 1001c0b0
- lfd 7ff0000000000000, -40 => 7ff0000000000000, 1001c0b0
- lfd fff0000000000000, -32 => fff0000000000000, 1001c0b0
- lfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 1001c0b0
- lfd fff7ffffffffffff, -16 => fff7ffffffffffff, 1001c0b0
- lfd 7ff8000000000000, -8 => 7ff8000000000000, 1001c0b0
- lfd 0010000000000001, 0 => 0010000000000001, 1001c038
- lfd 00100094e0000359, 8 => 00100094e0000359, 1001c038
- lfd 3fe0000000000001, 16 => 3fe0000000000001, 1001c038
- lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 1001c038
- lfd 8010000000000001, 32 => 8010000000000001, 1001c038
- lfd 80100094e0000359, 40 => 80100094e0000359, 1001c038
- lfd bfe0000000000001, 48 => bfe0000000000001, 1001c038
- lfd bfe00094e0000359, 56 => bfe00094e0000359, 1001c038
- lfd 0000000000000000, 64 => 0000000000000000, 1001c038
- lfd 8000000000000000, 72 => 8000000000000000, 1001c038
- lfd 7ff0000000000000, 80 => 7ff0000000000000, 1001c038
- lfd fff0000000000000, 88 => fff0000000000000, 1001c038
- lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 1001c038
- lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 1001c038
- lfd 7ff8000000000000, 112 => 7ff8000000000000, 1001c038
- lfd fff8000000000000, 120 => fff8000000000000, 1001c038
-
- lfdu 0010000000000001, -120 => 0010000000000001, 1001c038
- lfdu 00100094e0000359, -112 => 00100094e0000359, 1001c040
- lfdu 3fe0000000000001, -104 => 3fe0000000000001, 1001c048
- lfdu 3fe00094e0000359, -96 => 3fe00094e0000359, 1001c050
- lfdu 8010000000000001, -88 => 8010000000000001, 1001c058
- lfdu 80100094e0000359, -80 => 80100094e0000359, 1001c060
- lfdu bfe0000000000001, -72 => bfe0000000000001, 1001c068
- lfdu bfe00094e0000359, -64 => bfe00094e0000359, 1001c070
- lfdu 0000000000000000, -56 => 0000000000000000, 1001c078
- lfdu 8000000000000000, -48 => 8000000000000000, 1001c080
- lfdu 7ff0000000000000, -40 => 7ff0000000000000, 1001c088
- lfdu fff0000000000000, -32 => fff0000000000000, 1001c090
- lfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 1001c098
- lfdu fff7ffffffffffff, -16 => fff7ffffffffffff, 1001c0a0
- lfdu 7ff8000000000000, -8 => 7ff8000000000000, 1001c0a8
- lfdu 0010000000000001, 0 => 0010000000000001, 1001c038
- lfdu 00100094e0000359, 8 => 00100094e0000359, 1001c040
- lfdu 3fe0000000000001, 16 => 3fe0000000000001, 1001c048
- lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 1001c050
- lfdu 8010000000000001, 32 => 8010000000000001, 1001c058
- lfdu 80100094e0000359, 40 => 80100094e0000359, 1001c060
- lfdu bfe0000000000001, 48 => bfe0000000000001, 1001c068
- lfdu bfe00094e0000359, 56 => bfe00094e0000359, 1001c070
- lfdu 0000000000000000, 64 => 0000000000000000, 1001c078
- lfdu 8000000000000000, 72 => 8000000000000000, 1001c080
- lfdu 7ff0000000000000, 80 => 7ff0000000000000, 1001c088
- lfdu fff0000000000000, 88 => fff0000000000000, 1001c090
- lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 1001c098
- lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 1001c0a0
- lfdu 7ff8000000000000, 112 => 7ff8000000000000, 1001c0a8
- lfdu fff8000000000000, 120 => fff8000000000000, 1001c0b0
+ lfs 0010000000000001, -120 => 37e0000000000000, 0
+ lfs 00100094e0000359, -112 => 37e0009400000000, 0
+ lfs 3fe0000000000001, -104 => 3ffc000000000000, 0
+ lfs 3fe00094e0000359, -96 => 3ffc001280000000, 0
+ lfs 8010000000000001, -88 => b7e0000000000000, 0
+ lfs 80100094e0000359, -80 => b7e0009400000000, 0
+ lfs bfe0000000000001, -72 => bffc000000000000, 0
+ lfs bfe00094e0000359, -64 => bffc001280000000, 0
+ lfs 0000000000000000, -56 => 0000000000000000, 0
+ lfs 8000000000000000, -48 => 8000000000000000, 0
+ lfs 7ff0000000000000, -40 => 7ffe000000000000, 0
+ lfs fff0000000000000, -32 => fffe000000000000, 0
+ lfs 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0
+ lfs fff7ffffffffffff, -16 => fffeffffe0000000, 0
+ lfs 7ff8000000000000, -8 => 7fff000000000000, 0
+ lfs 0010000000000001, 0 => 37e0000000000000, 0
+ lfs 00100094e0000359, 8 => 37e0009400000000, 0
+ lfs 3fe0000000000001, 16 => 3ffc000000000000, 0
+ lfs 3fe00094e0000359, 24 => 3ffc001280000000, 0
+ lfs 8010000000000001, 32 => b7e0000000000000, 0
+ lfs 80100094e0000359, 40 => b7e0009400000000, 0
+ lfs bfe0000000000001, 48 => bffc000000000000, 0
+ lfs bfe00094e0000359, 56 => bffc001280000000, 0
+ lfs 0000000000000000, 64 => 0000000000000000, 0
+ lfs 8000000000000000, 72 => 8000000000000000, 0
+ lfs 7ff0000000000000, 80 => 7ffe000000000000, 0
+ lfs fff0000000000000, 88 => fffe000000000000, 0
+ lfs 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0
+ lfs fff7ffffffffffff, 104 => fffeffffe0000000, 0
+ lfs 7ff8000000000000, 112 => 7fff000000000000, 0
+ lfs fff8000000000000, 120 => ffff000000000000, 0
+
+ lfsu 0010000000000001, -120 => 37e0000000000000, -120
+ lfsu 00100094e0000359, -112 => 37e0009400000000, -112
+ lfsu 3fe0000000000001, -104 => 3ffc000000000000, -104
+ lfsu 3fe00094e0000359, -96 => 3ffc001280000000, -96
+ lfsu 8010000000000001, -88 => b7e0000000000000, -88
+ lfsu 80100094e0000359, -80 => b7e0009400000000, -80
+ lfsu bfe0000000000001, -72 => bffc000000000000, -72
+ lfsu bfe00094e0000359, -64 => bffc001280000000, -64
+ lfsu 0000000000000000, -56 => 0000000000000000, -56
+ lfsu 8000000000000000, -48 => 8000000000000000, -48
+ lfsu 7ff0000000000000, -40 => 7ffe000000000000, -40
+ lfsu fff0000000000000, -32 => fffe000000000000, -32
+ lfsu 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24
+ lfsu fff7ffffffffffff, -16 => fffeffffe0000000, -16
+ lfsu 7ff8000000000000, -8 => 7fff000000000000, -8
+ lfsu 0010000000000001, 0 => 37e0000000000000, 0
+ lfsu 00100094e0000359, 8 => 37e0009400000000, 8
+ lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16
+ lfsu 3fe00094e0000359, 24 => 3ffc001280000000, 24
+ lfsu 8010000000000001, 32 => b7e0000000000000, 32
+ lfsu 80100094e0000359, 40 => b7e0009400000000, 40
+ lfsu bfe0000000000001, 48 => bffc000000000000, 48
+ lfsu bfe00094e0000359, 56 => bffc001280000000, 56
+ lfsu 0000000000000000, 64 => 0000000000000000, 64
+ lfsu 8000000000000000, 72 => 8000000000000000, 72
+ lfsu 7ff0000000000000, 80 => 7ffe000000000000, 80
+ lfsu fff0000000000000, 88 => fffe000000000000, 88
+ lfsu 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96
+ lfsu fff7ffffffffffff, 104 => fffeffffe0000000, 104
+ lfsu 7ff8000000000000, 112 => 7fff000000000000, 112
+ lfsu fff8000000000000, 120 => ffff000000000000, 120
+
+ lfd 0010000000000001, -120 => 0010000000000001, 0
+ lfd 00100094e0000359, -112 => 00100094e0000359, 0
+ lfd 3fe0000000000001, -104 => 3fe0000000000001, 0
+ lfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
+ lfd 8010000000000001, -88 => 8010000000000001, 0
+ lfd 80100094e0000359, -80 => 80100094e0000359, 0
+ lfd bfe0000000000001, -72 => bfe0000000000001, 0
+ lfd bfe00094e0000359, -64 => bfe00094e0000359, 0
+ lfd 0000000000000000, -56 => 0000000000000000, 0
+ lfd 8000000000000000, -48 => 8000000000000000, 0
+ lfd 7ff0000000000000, -40 => 7ff0000000000000, 0
+ lfd fff0000000000000, -32 => fff0000000000000, 0
+ lfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
+ lfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
+ lfd 7ff8000000000000, -8 => 7ff8000000000000, 0
+ lfd 0010000000000001, 0 => 0010000000000001, 0
+ lfd 00100094e0000359, 8 => 00100094e0000359, 0
+ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
+ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
+ lfd 8010000000000001, 32 => 8010000000000001, 0
+ lfd 80100094e0000359, 40 => 80100094e0000359, 0
+ lfd bfe0000000000001, 48 => bfe0000000000001, 0
+ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0
+ lfd 0000000000000000, 64 => 0000000000000000, 0
+ lfd 8000000000000000, 72 => 8000000000000000, 0
+ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0
+ lfd fff0000000000000, 88 => fff0000000000000, 0
+ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
+ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
+ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
+ lfd fff8000000000000, 120 => fff8000000000000, 0
+
+ lfdu 0010000000000001, -120 => 0010000000000001, -120
+ lfdu 00100094e0000359, -112 => 00100094e0000359, -112
+ lfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
+ lfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
+ lfdu 8010000000000001, -88 => 8010000000000001, -88
+ lfdu 80100094e0000359, -80 => 80100094e0000359, -80
+ lfdu bfe0000000000001, -72 => bfe0000000000001, -72
+ lfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
+ lfdu 0000000000000000, -56 => 0000000000000000, -56
+ lfdu 8000000000000000, -48 => 8000000000000000, -48
+ lfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
+ lfdu fff0000000000000, -32 => fff0000000000000, -32
+ lfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
+ lfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
+ lfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
+ lfdu 0010000000000001, 0 => 0010000000000001, 0
+ lfdu 00100094e0000359, 8 => 00100094e0000359, 8
+ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
+ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
+ lfdu 8010000000000001, 32 => 8010000000000001, 32
+ lfdu 80100094e0000359, 40 => 80100094e0000359, 40
+ lfdu bfe0000000000001, 48 => bfe0000000000001, 48
+ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
+ lfdu 0000000000000000, 64 => 0000000000000000, 64
+ lfdu 8000000000000000, 72 => 8000000000000000, 72
+ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
+ lfdu fff0000000000000, 88 => fff0000000000000, 88
+ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
+ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
+ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
+ lfdu fff8000000000000, 120 => fff8000000000000, 120
PPC float load insns with two register args:
- lfsx 0010000000000001, -120 => 37e0000000000000, 1001c0b0
- lfsx 00100094e0000359, -112 => 37e0009400000000, 1001c0b0
- lfsx 3fe0000000000001, -104 => 3ffc000000000000, 1001c0b0
- lfsx 3fe00094e0000359, -96 => 3ffc001280000000, 1001c0b0
- lfsx 8010000000000001, -88 => b7e0000000000000, 1001c0b0
- lfsx 80100094e0000359, -80 => b7e0009400000000, 1001c0b0
- lfsx bfe0000000000001, -72 => bffc000000000000, 1001c0b0
- lfsx bfe00094e0000359, -64 => bffc001280000000, 1001c0b0
- lfsx 0000000000000000, -56 => 0000000000000000, 1001c0b0
- lfsx 8000000000000000, -48 => 8000000000000000, 1001c0b0
- lfsx 7ff0000000000000, -40 => 7ffe000000000000, 1001c0b0
- lfsx fff0000000000000, -32 => fffe000000000000, 1001c0b0
- lfsx 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 1001c0b0
- lfsx fff7ffffffffffff, -16 => fffeffffe0000000, 1001c0b0
- lfsx 7ff8000000000000, -8 => 7fff000000000000, 1001c0b0
- lfsx 0010000000000001, 0 => 37e0000000000000, 1001c038
- lfsx 00100094e0000359, 8 => 37e0009400000000, 1001c038
- lfsx 3fe0000000000001, 16 => 3ffc000000000000, 1001c038
- lfsx 3fe00094e0000359, 24 => 3ffc001280000000, 1001c038
- lfsx 8010000000000001, 32 => b7e0000000000000, 1001c038
- lfsx 80100094e0000359, 40 => b7e0009400000000, 1001c038
- lfsx bfe0000000000001, 48 => bffc000000000000, 1001c038
- lfsx bfe00094e0000359, 56 => bffc001280000000, 1001c038
- lfsx 0000000000000000, 64 => 0000000000000000, 1001c038
- lfsx 8000000000000000, 72 => 8000000000000000, 1001c038
- lfsx 7ff0000000000000, 80 => 7ffe000000000000, 1001c038
- lfsx fff0000000000000, 88 => fffe000000000000, 1001c038
- lfsx 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 1001c038
- lfsx fff7ffffffffffff, 104 => fffeffffe0000000, 1001c038
- lfsx 7ff8000000000000, 112 => 7fff000000000000, 1001c038
- lfsx fff8000000000000, 120 => ffff000000000000, 1001c038
-
- lfsux 0010000000000001, -120 => 37e0000000000000, 1001c038
- lfsux 00100094e0000359, -112 => 37e0009400000000, 1001c040
- lfsux 3fe0000000000001, -104 => 3ffc000000000000, 1001c048
- lfsux 3fe00094e0000359, -96 => 3ffc001280000000, 1001c050
- lfsux 8010000000000001, -88 => b7e0000000000000, 1001c058
- lfsux 80100094e0000359, -80 => b7e0009400000000, 1001c060
- lfsux bfe0000000000001, -72 => bffc000000000000, 1001c068
- lfsux bfe00094e0000359, -64 => bffc001280000000, 1001c070
- lfsux 0000000000000000, -56 => 0000000000000000, 1001c078
- lfsux 8000000000000000, -48 => 8000000000000000, 1001c080
- lfsux 7ff0000000000000, -40 => 7ffe000000000000, 1001c088
- lfsux fff0000000000000, -32 => fffe000000000000, 1001c090
- lfsux 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 1001c098
- lfsux fff7ffffffffffff, -16 => fffeffffe0000000, 1001c0a0
- lfsux 7ff8000000000000, -8 => 7fff000000000000, 1001c0a8
- lfsux 0010000000000001, 0 => 37e0000000000000, 1001c038
- lfsux 00100094e0000359, 8 => 37e0009400000000, 1001c040
- lfsux 3fe0000000000001, 16 => 3ffc000000000000, 1001c048
- lfsux 3fe00094e0000359, 24 => 3ffc001280000000, 1001c050
- lfsux 8010000000000001, 32 => b7e0000000000000, 1001c058
- lfsux 80100094e0000359, 40 => b7e0009400000000, 1001c060
- lfsux bfe0000000000001, 48 => bffc000000000000, 1001c068
- lfsux bfe00094e0000359, 56 => bffc001280000000, 1001c070
- lfsux 0000000000000000, 64 => 0000000000000000, 1001c078
- lfsux 8000000000000000, 72 => 8000000000000000, 1001c080
- lfsux 7ff0000000000000, 80 => 7ffe000000000000, 1001c088
- lfsux fff0000000000000, 88 => fffe000000000000, 1001c090
- lfsux 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 1001c098
- lfsux fff7ffffffffffff, 104 => fffeffffe0000000, 1001c0a0
- lfsux 7ff8000000000000, 112 => 7fff000000000000, 1001c0a8
- lfsux fff8000000000000, 120 => ffff000000000000, 1001c0b0
-
- lfdx 0010000000000001, -120 => 0010000000000001, 1001c0b0
- lfdx 00100094e0000359, -112 => 00100094e0000359, 1001c0b0
- lfdx 3fe0000000000001, -104 => 3fe0000000000001, 1001c0b0
- lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 1001c0b0
- lfdx 8010000000000001, -88 => 8010000000000001, 1001c0b0
- lfdx 80100094e0000359, -80 => 80100094e0000359, 1001c0b0
- lfdx bfe0000000000001, -72 => bfe0000000000001, 1001c0b0
- lfdx bfe00094e0000359, -64 => bfe00094e0000359, 1001c0b0
- lfdx 0000000000000000, -56 => 0000000000000000, 1001c0b0
- lfdx 8000000000000000, -48 => 8000000000000000, 1001c0b0
- lfdx 7ff0000000000000, -40 => 7ff0000000000000, 1001c0b0
- lfdx fff0000000000000, -32 => fff0000000000000, 1001c0b0
- lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 1001c0b0
- lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 1001c0b0
- lfdx 7ff8000000000000, -8 => 7ff8000000000000, 1001c0b0
- lfdx 0010000000000001, 0 => 0010000000000001, 1001c038
- lfdx 00100094e0000359, 8 => 00100094e0000359, 1001c038
- lfdx 3fe0000000000001, 16 => 3fe0000000000001, 1001c038
- lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 1001c038
- lfdx 8010000000000001, 32 => 8010000000000001, 1001c038
- lfdx 80100094e0000359, 40 => 80100094e0000359, 1001c038
- lfdx bfe0000000000001, 48 => bfe0000000000001, 1001c038
- lfdx bfe00094e0000359, 56 => bfe00094e0000359, 1001c038
- lfdx 0000000000000000, 64 => 0000000000000000, 1001c038
- lfdx 8000000000000000, 72 => 8000000000000000, 1001c038
- lfdx 7ff0000000000000, 80 => 7ff0000000000000, 1001c038
- lfdx fff0000000000000, 88 => fff0000000000000, 1001c038
- lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 1001c038
- lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 1001c038
- lfdx 7ff8000000000000, 112 => 7ff8000000000000, 1001c038
- lfdx fff8000000000000, 120 => fff8000000000000, 1001c038
-
- lfdux 0010000000000001, -120 => 0010000000000001, 1001c038
- lfdux 00100094e0000359, -112 => 00100094e0000359, 1001c040
- lfdux 3fe0000000000001, -104 => 3fe0000000000001, 1001c048
- lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, 1001c050
- lfdux 8010000000000001, -88 => 8010000000000001, 1001c058
- lfdux 80100094e0000359, -80 => 80100094e0000359, 1001c060
- lfdux bfe0000000000001, -72 => bfe0000000000001, 1001c068
- lfdux bfe00094e0000359, -64 => bfe00094e0000359, 1001c070
- lfdux 0000000000000000, -56 => 0000000000000000, 1001c078
- lfdux 8000000000000000, -48 => 8000000000000000, 1001c080
- lfdux 7ff0000000000000, -40 => 7ff0000000000000, 1001c088
- lfdux fff0000000000000, -32 => fff0000000000000, 1001c090
- lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 1001c098
- lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, 1001c0a0
- lfdux 7ff8000000000000, -8 => 7ff8000000000000, 1001c0a8
- lfdux 0010000000000001, 0 => 0010000000000001, 1001c038
- lfdux 00100094e0000359, 8 => 00100094e0000359, 1001c040
- lfdux 3fe0000000000001, 16 => 3fe0000000000001, 1001c048
- lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 1001c050
- lfdux 8010000000000001, 32 => 8010000000000001, 1001c058
- lfdux 80100094e0000359, 40 => 80100094e0000359, 1001c060
- lfdux bfe0000000000001, 48 => bfe0000000000001, 1001c068
- lfdux bfe00094e0000359, 56 => bfe00094e0000359, 1001c070
- lfdux 0000000000000000, 64 => 0000000000000000, 1001c078
- lfdux 8000000000000000, 72 => 8000000000000000, 1001c080
- lfdux 7ff0000000000000, 80 => 7ff0000000000000, 1001c088
- lfdux fff0000000000000, 88 => fff0000000000000, 1001c090
- lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 1001c098
- lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 1001c0a0
- lfdux 7ff8000000000000, 112 => 7ff8000000000000, 1001c0a8
- lfdux fff8000000000000, 120 => fff8000000000000, 1001c0b0
+ lfsx 0010000000000001, -120 => 37e0000000000000, 0
+ lfsx 00100094e0000359, -112 => 37e0009400000000, 0
+ lfsx 3fe0000000000001, -104 => 3ffc000000000000, 0
+ lfsx 3fe00094e0000359, -96 => 3ffc001280000000, 0
+ lfsx 8010000000000001, -88 => b7e0000000000000, 0
+ lfsx 80100094e0000359, -80 => b7e0009400000000, 0
+ lfsx bfe0000000000001, -72 => bffc000000000000, 0
+ lfsx bfe00094e0000359, -64 => bffc001280000000, 0
+ lfsx 0000000000000000, -56 => 0000000000000000, 0
+ lfsx 8000000000000000, -48 => 8000000000000000, 0
+ lfsx 7ff0000000000000, -40 => 7ffe000000000000, 0
+ lfsx fff0000000000000, -32 => fffe000000000000, 0
+ lfsx 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0
+ lfsx fff7ffffffffffff, -16 => fffeffffe0000000, 0
+ lfsx 7ff8000000000000, -8 => 7fff000000000000, 0
+ lfsx 0010000000000001, 0 => 37e0000000000000, 0
+ lfsx 00100094e0000359, 8 => 37e0009400000000, 0
+ lfsx 3fe0000000000001, 16 => 3ffc000000000000, 0
+ lfsx 3fe00094e0000359, 24 => 3ffc001280000000, 0
+ lfsx 8010000000000001, 32 => b7e0000000000000, 0
+ lfsx 80100094e0000359, 40 => b7e0009400000000, 0
+ lfsx bfe0000000000001, 48 => bffc000000000000, 0
+ lfsx bfe00094e0000359, 56 => bffc001280000000, 0
+ lfsx 0000000000000000, 64 => 0000000000000000, 0
+ lfsx 8000000000000000, 72 => 8000000000000000, 0
+ lfsx 7ff0000000000000, 80 => 7ffe000000000000, 0
+ lfsx fff0000000000000, 88 => fffe000000000000, 0
+ lfsx 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0
+ lfsx fff7ffffffffffff, 104 => fffeffffe0000000, 0
+ lfsx 7ff8000000000000, 112 => 7fff000000000000, 0
+ lfsx fff8000000000000, 120 => ffff000000000000, 0
+
+ lfsux 0010000000000001, -120 => 37e0000000000000, -120
+ lfsux 00100094e0000359, -112 => 37e0009400000000, -112
+ lfsux 3fe0000000000001, -104 => 3ffc000000000000, -104
+ lfsux 3fe00094e0000359, -96 => 3ffc001280000000, -96
+ lfsux 8010000000000001, -88 => b7e0000000000000, -88
+ lfsux 80100094e0000359, -80 => b7e0009400000000, -80
+ lfsux bfe0000000000001, -72 => bffc000000000000, -72
+ lfsux bfe00094e0000359, -64 => bffc001280000000, -64
+ lfsux 0000000000000000, -56 => 0000000000000000, -56
+ lfsux 8000000000000000, -48 => 8000000000000000, -48
+ lfsux 7ff0000000000000, -40 => 7ffe000000000000, -40
+ lfsux fff0000000000000, -32 => fffe000000000000, -32
+ lfsux 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24
+ lfsux fff7ffffffffffff, -16 => fffeffffe0000000, -16
+ lfsux 7ff8000000000000, -8 => 7fff000000000000, -8
+ lfsux 0010000000000001, 0 => 37e0000000000000, 0
+ lfsux 00100094e0000359, 8 => 37e0009400000000, 8
+ lfsux 3fe0000000000001, 16 => 3ffc000000000000, 16
+ lfsux 3fe00094e0000359, 24 => 3ffc001280000000, 24
+ lfsux 8010000000000001, 32 => b7e0000000000000, 32
+ lfsux 80100094e0000359, 40 => b7e0009400000000, 40
+ lfsux bfe0000000000001, 48 => bffc000000000000, 48
+ lfsux bfe00094e0000359, 56 => bffc001280000000, 56
+ lfsux 0000000000000000, 64 => 0000000000000000, 64
+ lfsux 8000000000000000, 72 => 8000000000000000, 72
+ lfsux 7ff0000000000000, 80 => 7ffe000000000000, 80
+ lfsux fff0000000000000, 88 => fffe000000000000, 88
+ lfsux 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96
+ lfsux fff7ffffffffffff, 104 => fffeffffe0000000, 104
+ lfsux 7ff8000000000000, 112 => 7fff000000000000, 112
+ lfsux fff8000000000000, 120 => ffff000000000000, 120
+
+ lfdx 0010000000000001, -120 => 0010000000000001, 0
+ lfdx 00100094e0000359, -112 => 00100094e0000359, 0
+ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0
+ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0
+ lfdx 8010000000000001, -88 => 8010000000000001, 0
+ lfdx 80100094e0000359, -80 => 80100094e0000359, 0
+ lfdx bfe0000000000001, -72 => bfe0000000000001, 0
+ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0
+ lfdx 0000000000000000, -56 => 0000000000000000, 0
+ lfdx 8000000000000000, -48 => 8000000000000000, 0
+ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0
+ lfdx fff0000000000000, -32 => fff0000000000000, 0
+ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
+ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0
+ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0
+ lfdx 0010000000000001, 0 => 0010000000000001, 0
+ lfdx 00100094e0000359, 8 => 00100094e0000359, 0
+ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
+ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
+ lfdx 8010000000000001, 32 => 8010000000000001, 0
+ lfdx 80100094e0000359, 40 => 80100094e0000359, 0
+ lfdx bfe0000000000001, 48 => bfe0000000000001, 0
+ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
+ lfdx 0000000000000000, 64 => 0000000000000000, 0
+ lfdx 8000000000000000, 72 => 8000000000000000, 0
+ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
+ lfdx fff0000000000000, 88 => fff0000000000000, 0
+ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
+ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
+ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
+ lfdx fff8000000000000, 120 => fff8000000000000, 0
+
+ lfdux 0010000000000001, -120 => 0010000000000001, -120
+ lfdux 00100094e0000359, -112 => 00100094e0000359, -112
+ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104
+ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96
+ lfdux 8010000000000001, -88 => 8010000000000001, -88
+ lfdux 80100094e0000359, -80 => 80100094e0000359, -80
+ lfdux bfe0000000000001, -72 => bfe0000000000001, -72
+ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64
+ lfdux 0000000000000000, -56 => 0000000000000000, -56
+ lfdux 8000000000000000, -48 => 8000000000000000, -48
+ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40
+ lfdux fff0000000000000, -32 => fff0000000000000, -32
+ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
+ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16
+ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8
+ lfdux 0010000000000001, 0 => 0010000000000001, 0
+ lfdux 00100094e0000359, 8 => 00100094e0000359, 8
+ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
+ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
+ lfdux 8010000000000001, 32 => 8010000000000001, 32
+ lfdux 80100094e0000359, 40 => 80100094e0000359, 40
+ lfdux bfe0000000000001, 48 => bfe0000000000001, 48
+ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
+ lfdux 0000000000000000, 64 => 0000000000000000, 64
+ lfdux 8000000000000000, 72 => 8000000000000000, 72
+ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
+ lfdux fff0000000000000, 88 => fff0000000000000, 88
+ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
+ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
+ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
+ lfdux fff8000000000000, 120 => fff8000000000000, 120
PPC float store insns
with one register + one 16 bits immediate args with flags update:
- stfs 0010000000000001, -56 => 0000000000000000, 1001c268
- stfs 00100094e0000359, -48 => 0000000000000000, 1001c268
- stfs 3fe0000000000001, -40 => 3f00000000000000, 1001c268
- stfs 3fe00094e0000359, -32 => 3f0004a700000000, 1001c268
- stfs 8010000000000001, -24 => 8000000000000000, 1001c268
- stfs 80100094e0000359, -16 => 8000000000000000, 1001c268
- stfs bfe0000000000001, -8 => bf00000000000000, 1001c268
- stfs 0010000000000001, 0 => 0000000000000000, 1001c230
- stfs 00100094e0000359, 8 => 0000000000000000, 1001c230
- stfs 3fe0000000000001, 16 => 3f00000000000000, 1001c230
- stfs 3fe00094e0000359, 24 => 3f0004a700000000, 1001c230
- stfs 8010000000000001, 32 => 8000000000000000, 1001c230
- stfs 80100094e0000359, 40 => 8000000000000000, 1001c230
- stfs bfe0000000000001, 48 => bf00000000000000, 1001c230
- stfs bfe00094e0000359, 56 => bf0004a700000000, 1001c230
-
- stfsu 0010000000000001, -56 => 0000000000000000, 1001c230
- stfsu 00100094e0000359, -48 => 0000000000000000, 1001c238
- stfsu 3fe0000000000001, -40 => 3f00000000000000, 1001c240
- stfsu 3fe00094e0000359, -32 => 3f0004a700000000, 1001c248
- stfsu 8010000000000001, -24 => 8000000000000000, 1001c250
- stfsu 80100094e0000359, -16 => 8000000000000000, 1001c258
- stfsu bfe0000000000001, -8 => bf00000000000000, 1001c260
- stfsu 0010000000000001, 0 => 0000000000000000, 1001c230
- stfsu 00100094e0000359, 8 => 0000000000000000, 1001c238
- stfsu 3fe0000000000001, 16 => 3f00000000000000, 1001c240
- stfsu 3fe00094e0000359, 24 => 3f0004a700000000, 1001c248
- stfsu 8010000000000001, 32 => 8000000000000000, 1001c250
- stfsu 80100094e0000359, 40 => 8000000000000000, 1001c258
- stfsu bfe0000000000001, 48 => bf00000000000000, 1001c260
- stfsu bfe00094e0000359, 56 => bf0004a700000000, 1001c268
-
- stfd 0010000000000001, -120 => 0010000000000001, 1001c2f0
- stfd 00100094e0000359, -112 => 00100094e0000359, 1001c2f0
- stfd 3fe0000000000001, -104 => 3fe0000000000001, 1001c2f0
- stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 1001c2f0
- stfd 8010000000000001, -88 => 8010000000000001, 1001c2f0
- stfd 80100094e0000359, -80 => 80100094e0000359, 1001c2f0
- stfd bfe0000000000001, -72 => bfe0000000000001, 1001c2f0
- stfd bfe00094e0000359, -64 => bfe00094e0000359, 1001c2f0
- stfd 0000000000000000, -56 => 0000000000000000, 1001c2f0
- stfd 8000000000000000, -48 => 8000000000000000, 1001c2f0
- stfd 7ff0000000000000, -40 => 7ff0000000000000, 1001c2f0
- stfd fff0000000000000, -32 => fff0000000000000, 1001c2f0
- stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 1001c2f0
- stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 1001c2f0
- stfd 7ff8000000000000, -8 => 7ff8000000000000, 1001c2f0
- stfd 0010000000000001, 0 => 0010000000000001, 1001c278
- stfd 00100094e0000359, 8 => 00100094e0000359, 1001c278
- stfd 3fe0000000000001, 16 => 3fe0000000000001, 1001c278
- stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 1001c278
- stfd 8010000000000001, 32 => 8010000000000001, 1001c278
- stfd 80100094e0000359, 40 => 80100094e0000359, 1001c278
- stfd bfe0000000000001, 48 => bfe0000000000001, 1001c278
- stfd bfe00094e0000359, 56 => bfe00094e0000359, 1001c278
- stfd 0000000000000000, 64 => 0000000000000000, 1001c278
- stfd 8000000000000000, 72 => 8000000000000000, 1001c278
- stfd 7ff0000000000000, 80 => 7ff0000000000000, 1001c278
- stfd fff0000000000000, 88 => fff0000000000000, 1001c278
- stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 1001c278
- stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 1001c278
- stfd 7ff8000000000000, 112 => 7ff8000000000000, 1001c278
- stfd fff8000000000000, 120 => fff8000000000000, 1001c278
-
- stfdu 0010000000000001, -120 => 0010000000000001, 1001c208
- stfdu 00100094e0000359, -112 => 00100094e0000359, 1001c210
- stfdu 3fe0000000000001, -104 => 3fe0000000000001, 1001c218
- stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, 1001c220
- stfdu 8010000000000001, -88 => 8010000000000001, 1001c228
- stfdu 80100094e0000359, -80 => 80100094e0000359, 1001c230
- stfdu bfe0000000000001, -72 => bfe0000000000001, 1001c238
- stfdu bfe00094e0000359, -64 => bfe00094e0000359, 1001c240
- stfdu 0000000000000000, -56 => 0000000000000000, 1001c248
- stfdu 8000000000000000, -48 => 8000000000000000, 1001c250
- stfdu 7ff0000000000000, -40 => 7ff0000000000000, 1001c258
- stfdu fff0000000000000, -32 => fff0000000000000, 1001c260
- stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 1001c268
- stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, 1001c270
- stfdu 7ff8000000000000, -8 => 7ff8000000000000, 1001c278
- stfdu 0010000000000001, 0 => 0010000000000001, 1001c208
- stfdu 00100094e0000359, 8 => 00100094e0000359, 1001c210
- stfdu 3fe0000000000001, 16 => 3fe0000000000001, 1001c218
- stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 1001c220
- stfdu 8010000000000001, 32 => 8010000000000001, 1001c228
- stfdu 80100094e0000359, 40 => 80100094e0000359, 1001c230
- stfdu bfe0000000000001, 48 => bfe0000000000001, 1001c238
- stfdu bfe00094e0000359, 56 => bfe00094e0000359, 1001c240
- stfdu 0000000000000000, 64 => 0000000000000000, 1001c248
- stfdu 8000000000000000, 72 => 8000000000000000, 1001c250
- stfdu 7ff0000000000000, 80 => 7ff0000000000000, 1001c258
- stfdu fff0000000000000, 88 => fff0000000000000, 1001c260
- stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 1001c268
- stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 1001c270
- stfdu 7ff8000000000000, 112 => 7ff8000000000000, 1001c278
- stfdu fff8000000000000, 120 => fff8000000000000, 1001c280
+ stfs 0010000000000001, -56 => 0000000000000000, 0
+ stfs 00100094e0000359, -48 => 0000000000000000, 0
+ stfs 3fe0000000000001, -40 => 3f00000000000000, 0
+ stfs 3fe00094e0000359, -32 => 3f0004a700000000, 0
+ stfs 8010000000000001, -24 => 8000000000000000, 0
+ stfs 80100094e0000359, -16 => 8000000000000000, 0
+ stfs bfe0000000000001, -8 => bf00000000000000, 0
+ stfs 0010000000000001, 0 => 0000000000000000, 0
+ stfs 00100094e0000359, 8 => 0000000000000000, 0
+ stfs 3fe0000000000001, 16 => 3f00000000000000, 0
+ stfs 3fe00094e0000359, 24 => 3f0004a700000000, 0
+ stfs 8010000000000001, 32 => 8000000000000000, 0
+ stfs 80100094e0000359, 40 => 8000000000000000, 0
+ stfs bfe0000000000001, 48 => bf00000000000000, 0
+ stfs bfe00094e0000359, 56 => bf0004a700000000, 0
+
+ stfsu 0010000000000001, -56 => 0000000000000000, -56
+ stfsu 00100094e0000359, -48 => 0000000000000000, -48
+ stfsu 3fe0000000000001, -40 => 3f00000000000000, -40
+ stfsu 3fe00094e0000359, -32 => 3f0004a700000000, -32
+ stfsu 8010000000000001, -24 => 8000000000000000, -24
+ stfsu 80100094e0000359, -16 => 8000000000000000, -16
+ stfsu bfe0000000000001, -8 => bf00000000000000, -8
+ stfsu 0010000000000001, 0 => 0000000000000000, 0
+ stfsu 00100094e0000359, 8 => 0000000000000000, 8
+ stfsu 3fe0000000000001, 16 => 3f00000000000000, 16
+ stfsu 3fe00094e0000359, 24 => 3f0004a700000000, 24
+ stfsu 8010000000000001, 32 => 8000000000000000, 32
+ stfsu 80100094e0000359, 40 => 8000000000000000, 40
+ stfsu bfe0000000000001, 48 => bf00000000000000, 48
+ stfsu bfe00094e0000359, 56 => bf0004a700000000, 56
+
+ stfd 0010000000000001, -120 => 0010000000000001, 0
+ stfd 00100094e0000359, -112 => 00100094e0000359, 0
+ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0
+ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
+ stfd 8010000000000001, -88 => 8010000000000001, 0
+ stfd 80100094e0000359, -80 => 80100094e0000359, 0
+ stfd bfe0000000000001, -72 => bfe0000000000001, 0
+ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0
+ stfd 0000000000000000, -56 => 0000000000000000, 0
+ stfd 8000000000000000, -48 => 8000000000000000, 0
+ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0
+ stfd fff0000000000000, -32 => fff0000000000000, 0
+ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
+ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
+ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0
+ stfd 0010000000000001, 0 => 0010000000000001, 0
+ stfd 00100094e0000359, 8 => 00100094e0000359, 0
+ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0
+ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
+ stfd 8010000000000001, 32 => 8010000000000001, 0
+ stfd 80100094e0000359, 40 => 80100094e0000359, 0
+ stfd bfe0000000000001, 48 => bfe0000000000001, 0
+ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0
+ stfd 0000000000000000, 64 => 0000000000000000, 0
+ stfd 8000000000000000, 72 => 8000000000000000, 0
+ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0
+ stfd fff0000000000000, 88 => fff0000000000000, 0
+ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
+ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
+ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0
+ stfd fff8000000000000, 120 => fff8000000000000, 0
+
+ stfdu 0010000000000001, -120 => 0010000000000001, -120
+ stfdu 00100094e0000359, -112 => 00100094e0000359, -112
+ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
+ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
+ stfdu 8010000000000001, -88 => 8010000000000001, -88
+ stfdu 80100094e0000359, -80 => 80100094e0000359, -80
+ stfdu bfe0000000000001, -72 => bfe0000000000001, -72
+ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
+ stfdu 0000000000000000, -56 => 0000000000000000, -56
+ stfdu 8000000000000000, -48 => 8000000000000000, -48
+ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
+ stfdu fff0000000000000, -32 => fff0000000000000, -32
+ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
+ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
+ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
+ stfdu 0010000000000001, 0 => 0010000000000001, 0
+ stfdu 00100094e0000359, 8 => 00100094e0000359, 8
+ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
+ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
+ stfdu 8010000000000001, 32 => 8010000000000001, 32
+ stfdu 80100094e0000359, 40 => 80100094e0000359, 40
+ stfdu bfe0000000000001, 48 => bfe0000000000001, 48
+ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
+ stfdu 0000000000000000, 64 => 0000000000000000, 64
+ stfdu 8000000000000000, 72 => 8000000000000000, 72
+ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
+ stfdu fff0000000000000, 88 => fff0000000000000, 88
+ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
+ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
+ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
+ stfdu fff8000000000000, 120 => fff8000000000000, 120
PPC float store insns with three register args:
- stfsx 0010000000000001, 0 => 0000000000000000, 1001c208
- stfsx 00100094e0000359, 8 => 0000000000000000, 1001c208
- stfsx 3fe0000000000001, 16 => 3f00000000000000, 1001c208
- stfsx 3fe00094e0000359, 24 => 3f0004a700000000, 1001c208
- stfsx 8010000000000001, 32 => 8000000000000000, 1001c208
- stfsx 80100094e0000359, 40 => 8000000000000000, 1001c208
- stfsx bfe0000000000001, 48 => bf00000000000000, 1001c208
- stfsx bfe00094e0000359, 56 => bf0004a700000000, 1001c208
-
- stfsux 0010000000000001, 0 => 0000000000000000, 1001c208
- stfsux 00100094e0000359, 8 => 0000000000000000, 1001c210
- stfsux 3fe0000000000001, 16 => 3f00000000000000, 1001c218
- stfsux 3fe00094e0000359, 24 => 3f0004a700000000, 1001c220
- stfsux 8010000000000001, 32 => 8000000000000000, 1001c228
- stfsux 80100094e0000359, 40 => 8000000000000000, 1001c230
- stfsux bfe0000000000001, 48 => bf00000000000000, 1001c238
- stfsux bfe00094e0000359, 56 => bf0004a700000000, 1001c240
-
- stfdx 0010000000000001, 0 => 0010000000000001, 1001c250
- stfdx 00100094e0000359, 8 => 00100094e0000359, 1001c250
- stfdx 3fe0000000000001, 16 => 3fe0000000000001, 1001c250
- stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 1001c250
- stfdx 8010000000000001, 32 => 8010000000000001, 1001c250
- stfdx 80100094e0000359, 40 => 80100094e0000359, 1001c250
- stfdx bfe0000000000001, 48 => bfe0000000000001, 1001c250
- stfdx bfe00094e0000359, 56 => bfe00094e0000359, 1001c250
- stfdx 0000000000000000, 64 => 0000000000000000, 1001c250
- stfdx 8000000000000000, 72 => 8000000000000000, 1001c250
- stfdx 7ff0000000000000, 80 => 7ff0000000000000, 1001c250
- stfdx fff0000000000000, 88 => fff0000000000000, 1001c250
- stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 1001c250
- stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 1001c250
- stfdx 7ff8000000000000, 112 => 7ff8000000000000, 1001c250
- stfdx fff8000000000000, 120 => fff8000000000000, 1001c250
-
- stfdux 0010000000000001, 0 => 0010000000000001, 1001c208
- stfdux 00100094e0000359, 8 => 00100094e0000359, 1001c210
- stfdux 3fe0000000000001, 16 => 3fe0000000000001, 1001c218
- stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 1001c220
- stfdux 8010000000000001, 32 => 8010000000000001, 1001c228
- stfdux 80100094e0000359, 40 => 80100094e0000359, 1001c230
- stfdux bfe0000000000001, 48 => bfe0000000000001, 1001c238
- stfdux bfe00094e0000359, 56 => bfe00094e0000359, 1001c240
- stfdux 0000000000000000, 64 => 0000000000000000, 1001c248
- stfdux 8000000000000000, 72 => 8000000000000000, 1001c250
- stfdux 7ff0000000000000, 80 => 7ff0000000000000, 1001c258
- stfdux fff0000000000000, 88 => fff0000000000000, 1001c260
- stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 1001c268
- stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 1001c270
- stfdux 7ff8000000000000, 112 => 7ff8000000000000, 1001c278
- stfdux fff8000000000000, 120 => fff8000000000000, 1001c280
+ stfsx 0010000000000001, 0 => 0000000000000000, 0
+ stfsx 00100094e0000359, 8 => 0000000000000000, 0
+ stfsx 3fe0000000000001, 16 => 3f00000000000000, 0
+ stfsx 3fe00094e0000359, 24 => 3f0004a700000000, 0
+ stfsx 8010000000000001, 32 => 8000000000000000, 0
+ stfsx 80100094e0000359, 40 => 8000000000000000, 0
+ stfsx bfe0000000000001, 48 => bf00000000000000, 0
+ stfsx bfe00094e0000359, 56 => bf0004a700000000, 0
+
+ stfsux 0010000000000001, 0 => 0000000000000000, 0
+ stfsux 00100094e0000359, 8 => 0000000000000000, 8
+ stfsux 3fe0000000000001, 16 => 3f00000000000000, 16
+ stfsux 3fe00094e0000359, 24 => 3f0004a700000000, 24
+ stfsux 8010000000000001, 32 => 8000000000000000, 32
+ stfsux 80100094e0000359, 40 => 8000000000000000, 40
+ stfsux bfe0000000000001, 48 => bf00000000000000, 48
+ stfsux bfe00094e0000359, 56 => bf0004a700000000, 56
+
+ stfdx 0010000000000001, 0 => 0010000000000001, 0
+ stfdx 00100094e0000359, 8 => 00100094e0000359, 0
+ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
+ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
+ stfdx 8010000000000001, 32 => 8010000000000001, 0
+ stfdx 80100094e0000359, 40 => 80100094e0000359, 0
+ stfdx bfe0000000000001, 48 => bfe0000000000001, 0
+ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
+ stfdx 0000000000000000, 64 => 0000000000000000, 0
+ stfdx 8000000000000000, 72 => 8000000000000000, 0
+ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
+ stfdx fff0000000000000, 88 => fff0000000000000, 0
+ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
+ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
+ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
+ stfdx fff8000000000000, 120 => fff8000000000000, 0
+
+ stfdux 0010000000000001, 0 => 0010000000000001, 0
+ stfdux 00100094e0000359, 8 => 00100094e0000359, 8
+ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
+ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
+ stfdux 8010000000000001, 32 => 8010000000000001, 32
+ stfdux 80100094e0000359, 40 => 80100094e0000359, 40
+ stfdux bfe0000000000001, 48 => bfe0000000000001, 48
+ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
+ stfdux 0000000000000000, 64 => 0000000000000000, 64
+ stfdux 8000000000000000, 72 => 8000000000000000, 72
+ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
+ stfdux fff0000000000000, 88 => fff0000000000000, 88
+ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
+ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
+ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
+ stfdux fff8000000000000, 120 => fff8000000000000, 120
All done. Tested 67 different instructions
/* These should be set at build time */
//#define NO_FLOAT
-//#define HAS_ALTIVEC
+//#define HAS_ALTIVEC // CFLAGS += -maltivec
//#define IS_PPC405
/**********************************************************************/
# include <altivec.h>
#endif
#include <assert.h>
-#include <ctype.h>
-#include <fcntl.h>
+#include <ctype.h> // isspace
+//#include <fcntl.h>
//#include <fenv.h>
//#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
-#include <unistd.h>
+#include <unistd.h> // getopt
#include <malloc.h>
)
+
/* -------------- BEGIN #include "test-ppc.h" -------------- */
/*
* test-ppc.h:
int i=0;
if (arg_list_size == 1) { // Large
- iargs = malloc(400 * sizeof(uint32_t));
+ iargs = malloc(400 * sizeof(HWord_t));
for (tmp=0; ; tmp = tmp + 1 + (tmp >> 1)) {
if (tmp >= 0x100000000ULL)
tmp = 0xFFFFFFFF;
- iargs[i++] = (uint32_t)tmp;
- AB_DPRINTF("val %08x\n", (uint32_t)tmp);
+ iargs[i++] = (HWord_t)tmp;
+ AB_DPRINTF("val %08x\n", (HWord_t)tmp);
if (tmp == 0xFFFFFFFF)
break;
}
} else { // Default
- iargs = malloc(10 * sizeof(uint32_t));
+ iargs = malloc(10 * sizeof(HWord_t));
// for (tmp = 0; ; tmp = 71*tmp + 1 + (tmp>>1)) { // gives 8
// for (tmp = 0; ; tmp = 100000*tmp + 1 + (tmp>>1)) { // gives 4
for (tmp=0; ; tmp = 999999*tmp + 999999) { // gives 3
if (tmp >= 0x100000000ULL)
tmp = 0xFFFFFFFF;
- iargs[i++] = (uint32_t)tmp;
- AB_DPRINTF("val %08x\n", (uint32_t)tmp);
+ iargs[i++] = (HWord_t)tmp;
+ AB_DPRINTF("val %08x\n", (HWord_t)tmp);
if (tmp == 0xFFFFFFFF)
break;
}
if (tmp >= 0x10000)
tmp = 0xFFFF;
ii16[i++] = tmp;
- AB_DPRINTF("val %08x\n", tmp);
+ AB_DPRINTF("val %04x\n", tmp);
if (tmp == 0xFFFF)
break;
}
if (tmp >= 0x10000)
tmp = 0xFFFF;
ii16[i++] = tmp;
- AB_DPRINTF("val %08x\n", tmp);
+ AB_DPRINTF("val %04x\n", tmp);
if (tmp == 0xFFFF)
break;
}
r14 = iargs[i];
r15 = iargs[j];
r16 = iargs[k];
+
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
__asm__ __volatile__ ("mfxer 18");
xer = r18;
res = r17;
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %08x, %08x, %08x => %08x (%08x %08x)\n",
name, iargs[i], iargs[j], iargs[k], res, flags, xer);
}
{
volatile HWord_t res;
volatile uint32_t flags, xer, xer_orig, tmpcr, tmpxer;
- int i, j, is_div;
+ int i, j, is_div, zap_hi32;
// catches div, divwu, divo, divwu, divwuo, and . variants
is_div = strstr(name, "divw") != NULL;
+
+ zap_hi32 = strstr(name, "mulhw") != NULL;
xer_orig = 0x00000000;
redo:
don't test it. */
if (is_div && iargs[j] == 0)
continue;
+
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
__asm__ __volatile__ ("mfxer 18");
xer = r18;
res = r17;
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %08x, %08x => %08x (%08x %08x)\n",
name, iargs[i], iargs[j], res, flags, xer);
}
redo:
for (i=0; i<nb_iargs; i++) {
r14 = iargs[i];
+
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
flags = r18;
__asm__ __volatile__ ("mfxer 18");
xer = r18;
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %08x => %08x (%08x %08x)\n",
name, iargs[i], res, flags, xer);
}
for (i=0; i<nb_iargs; i++) {
for (j=0; j<nb_ii16; j++) {
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
patch_op_imm16(&func_buf[0], ii16[j]);
r14 = iargs[i];
+
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
__asm__ __volatile__ ("mfxer 18");
xer = r18;
res = r17;
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %08x, %08x => %08x (%08x %08x)\n",
name, iargs[i], ii16[j], res, flags, xer);
}
arg_step = (arg_list_size == 0) ? 31 : 3;
+ r17 = 0; // rlwimi takes r17 as input: start with a clean slate.
+
for (i=0; i<nb_iargs; i++) {
for (j=0; j<32; j+=arg_step) {
for (k=0; k<32; k+=arg_step) {
for (l=0; l<32; l+=arg_step) {
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
_patch_op_imm(&func_buf[0], j, 11, 5);
_patch_op_imm(&func_buf[0], k, 6, 5);
patch_op_imm(&func_buf[0], l, 1, 5);
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %08x, %2d, %2d, %2d => %08x (%08x %08x)\n",
name, iargs[i], j, k, l, res, flags, xer);
}
for (j=0; j<nb_iargs; j++) {
for (k=0; k<32; k+=arg_step) {
for (l=0; l<32; l+=arg_step) {
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
_patch_op_imm(&func_buf[0], k, 6, 5);
patch_op_imm(&func_buf[0], l, 1, 5);
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %08x, %08x, %2d, %2d => %08x (%08x %08x)\n",
name, iargs[i], iargs[j], k, l, res, flags, xer);
}
for (i=0; i<nb_iargs; i++) {
for (j=0; j<32; j+=arg_step) {
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
patch_op_imm(&func_buf[0], j, 11, 5);
r14 = iargs[i];
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %08x, %2d => %08x (%08x %08x)\n",
name, iargs[i], j, res, flags, xer);
}
volatile uint32_t flags, xer, tmpcr, tmpxer;
int i, j, k, arg_step;
-
arg_step = (arg_list_size == 0) ? 7 : 1;
for (i=0; i<nb_iargs; i++) {
for (j=0; j<8; j+=arg_step) {
for (k=0; k<8; k+=arg_step) {
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
_patch_op_imm(&func_buf[0], j, 23, 3);
patch_op_imm(&func_buf[0], k, 18, 3);
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %d, %d (%08x) => (%08x %08x)\n",
name, j, k, iargs[i], flags, xer);
}
for (i=0; i<16; i+=arg_step) {
j = i << 28;
for (k=0; k<8; k+=arg_step) {
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
patch_op_imm(&func_buf[0], k, 23, 3);
r14 = j;
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %d (%08x) => (%08x %08x)\n",
name, k, j, flags, xer);
}
for (i=0; i<nb_iargs; i++) {
r14 = iargs[i];
+
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 14");
__asm__ __volatile__ ("mfxer 18");
xer = r18;
res = r17;
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s (%08x) => %08x (%08x %08x)\n",
name, iargs[i], res, flags, xer);
}
unused uint32_t test_flags)
{
//volatile uint32_t res, flags, xer, ctr, lr, tmpcr, tmpxer;
- int j, k, res;
+ volatile HWord_t res;
+ int j, k;
func = func; // just to stop compiler complaining
-
+
// mtxer followed by mfxer
for (k=0; k<nb_iargs; k++) {
j = iargs[k];
: /*out*/"=r"(res) : /*in*/"r"(j) : /*trashed*/"xer"
);
res &= 0xE000007F; /* rest of the bits are undefined */
+
printf("%s 1 (%08x) -> mtxer -> mfxer => %08x\n",
name, j, res);
}
"\tmflr %0"
: /*out*/"=r"(res) : /*in*/"r"(j) : /*trashed*/"lr"
);
+
printf("%s 8 (%08x) -> mtlr -> mflr => %08x\n",
name, j, res);
}
"\tmfctr %0"
: /*out*/"=r"(res) : /*in*/"r"(j) : /*trashed*/"ctr"
);
+
printf("%s 9 (%08x) -> mtctr -> mfctr => %08x\n",
name, j, res);
}
j = 1;
for (k=0; k<nb_iargs; k++) {
r14 = iargs[k];
+
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
__asm__ __volatile__ ("mfxer 18");
xer = r18;
res = r17;
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %d => %08x (%08x %08x)\n",
name, i, res, flags, xer);
}
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
__asm__ __volatile__ ("mfxer 18");
xer = r18;
res = r17;
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %d => %08x (%08x %08x)\n",
name, i, res, flags, xer);
}
for (i=0; i<nb_iargs; i++) {
for (j=0; j<256; j+=arg_step) {
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
patch_op_imm(&func_buf[0], j, 12, 8);
r14 = iargs[i];
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %3d, %08x => (%08x %08x)\n",
name, j, iargs[i], flags, xer);
}
unused uint32_t test_flags)
{
uint32_t func_buf[2];
- volatile HWord_t res, rA;
+ volatile HWord_t res, base;
volatile uint32_t flags, xer, tmpcr, tmpxer;
- int i, j;
-
+ int i, offs;
+
// +ve d
+ base = (HWord_t)&iargs[0];
for (i=0; i<nb_iargs; i++) {
- j = i * sizeof(HWord_t);
+ offs = i * sizeof(HWord_t);
- init_function( &func, func_buf );
/* Patch up the instruction */
- patch_op_imm16(&func_buf[0], j);
+ init_function( &func, func_buf );
+ patch_op_imm16(&func_buf[0], offs);
- r14 = (HWord_t)&iargs[0]; // base reg = start of array
+ r14 = base;
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
__asm__ __volatile__ ("mfxer 18");
xer = r18;
res = r17;
- rA = r14;
/* Restore flags */
r18 = tmpcr;
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
- printf("%s %2d, (%08x) => %08x (%08x %08x)\n",
- name, j, /*&iargs[0], */ iargs[i], res, /*rA, */ flags, xer);
+ printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
+ name, offs, iargs[i], res, r14-base, flags, xer);
}
if (verbose) printf("\n");
// -ve d
+ base = (HWord_t)&iargs[nb_iargs-1];
for (i = -nb_iargs+1; i<=0; i++) {
- j = i * sizeof(HWord_t);
+ offs = i * sizeof(HWord_t);
- init_function( &func, func_buf );
/* Patch up the instruction */
- patch_op_imm16(&func_buf[0], j);
+ init_function( &func, func_buf );
+ patch_op_imm16(&func_buf[0], offs);
- r14 = (HWord_t)&iargs[nb_iargs-1];
+ r14 = base;
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
__asm__ __volatile__ ("mfxer 18");
xer = r18;
res = r17;
- rA = r14;
/* Restore flags */
r18 = tmpcr;
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
- printf("%s %2d, (%08x) => %08x (%08x %08x)\n",
- name, j, /*&iargs[nb_iargs-1], */ iargs[nb_iargs-1+i], res, /*rA, */ flags, xer);
+ printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
+ name, offs, iargs[nb_iargs-1+i], res, r14-base, flags, xer);
}
}
test_func_t func,
unused uint32_t test_flags)
{
- volatile HWord_t res, rA;
+ volatile HWord_t res, base;
volatile uint32_t flags, xer, tmpcr, tmpxer;
- int i, j;
+ int i, offs;
// +ve d
+ base = (HWord_t)&iargs[0];
for (i=0; i<nb_iargs; i++) {
- j = i * sizeof(HWord_t);
- r14 = (HWord_t)&iargs[0];
- r15 = j;
+ offs = i * sizeof(HWord_t);
+ r14 = base;
+ r15 = offs;
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
__asm__ __volatile__ ("mfxer 18");
xer = r18;
res = r17;
- rA = r14;
/* Restore flags */
r18 = tmpcr;
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
- printf("%s %d (%08x) => %08x (%08x %08x)\n",
- name, /*&iargs[0], */ j, iargs[i], res, /*rA, */ flags, xer);
+ printf("%s %d (%08x) => %08x, %d (%08x %08x)\n",
+ name, offs, iargs[i], res, r14-base, flags, xer);
}
}
unused uint32_t test_flags)
{
uint32_t func_buf[2];
- volatile HWord_t rA;
volatile uint32_t flags, xer, tmpcr, tmpxer;
- int i, j, k;
- HWord_t *iargs_priv;
-
+ int i, offs, k;
+ HWord_t *iargs_priv, base;
+
// private iargs table to store to
iargs_priv = malloc(nb_iargs * sizeof(HWord_t));
- // __asm__ __volatile__ ("stwu 14,0(15)");
-
// +ve d
+ base = (HWord_t)&iargs_priv[0];
for (i=0; i<nb_iargs; i++) {
for (k=0; k<nb_iargs; k++) // clear array
iargs_priv[k] = 0;
- j = i * sizeof(HWord_t);
-
- init_function( &func, func_buf );
+ offs = i * sizeof(HWord_t);
+
/* Patch up the instruction */
- patch_op_imm16(&func_buf[0], j);
+ init_function( &func, func_buf );
+ patch_op_imm16(&func_buf[0], offs);
- r14 = iargs[i]; // read from iargs
- r15 = (HWord_t)&iargs_priv[0]; // store to r15 + j
+ r14 = iargs[i]; // read from iargs
+ r15 = base; // store to r15 + offs
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
flags = r18;
__asm__ __volatile__ ("mfxer 18");
xer = r18;
- rA = r15;
/* Restore flags */
r18 = tmpcr;
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
- printf("%s %08x, %2d => %08x (%08x %08x)\n",
- name, iargs[i], j, /*&iargs_priv[0], */ iargs_priv[i], /*rA, */ flags, xer);
+ printf("%s %08x, %2d => %08x, %2d (%08x %08x)\n",
+ name, iargs[i], offs, iargs_priv[i], r15-base, flags, xer);
}
if (verbose) printf("\n");
// -ve d
+ base = (HWord_t)&iargs_priv[nb_iargs-1];
for (i = -nb_iargs+1; i<=0; i++) {
for (k=0; k<nb_iargs; k++) // clear array
iargs_priv[k] = 0;
- j = i * sizeof(HWord_t);
-
- init_function( &func, func_buf );
+ offs = i * sizeof(HWord_t);
+
/* Patch up the instruction */
- patch_op_imm16(&func_buf[0], j);
+ init_function( &func, func_buf );
+ patch_op_imm16(&func_buf[0], offs);
- r14 = iargs[nb_iargs-1+i]; // read from iargs
- r15 = (HWord_t)&iargs_priv[nb_iargs-1]; // store to r15 + j
+ r14 = iargs[nb_iargs-1+i]; // read from iargs
+ r15 = base; // store to r15 + offs
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
flags = r18;
__asm__ __volatile__ ("mfxer 18");
xer = r18;
- rA = r15;
/* Restore flags */
r18 = tmpcr;
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
- printf("%s %08x, %2d => %08x (%08x %08x)\n",
- name, iargs[nb_iargs-1+i], j, /*&iargs_priv[nb_iargs-1], */ iargs_priv[nb_iargs-1+i], /*rA, */ flags, xer);
+ printf("%s %08x, %2d => %08x, %2d (%08x %08x)\n",
+ name, iargs[nb_iargs-1+i], offs, iargs_priv[nb_iargs-1+i],
+ r15-base, flags, xer);
}
free(iargs_priv);
}
test_func_t func,
unused uint32_t test_flags)
{
- volatile HWord_t rA;
volatile uint32_t flags, xer, tmpcr, tmpxer;
- int i, j, k;
- HWord_t *iargs_priv;
-
+ int i, offs, k;
+ HWord_t *iargs_priv, base;
+
// private iargs table to store to
iargs_priv = malloc(nb_iargs * sizeof(HWord_t));
+ base = (HWord_t)&iargs_priv[0];
for (i=0; i<nb_iargs; i++) {
for (k=0; k<nb_iargs; k++) // clear array
iargs_priv[k] = 0;
- j = i * sizeof(HWord_t);
- r14 = iargs[i]; // read from iargs
- r15 = (HWord_t)&iargs_priv[0]; // store to r15 + j
- r16 = j;
+ offs = i * sizeof(HWord_t);
+ r14 = iargs[i]; // read from iargs
+ r15 = base; // store to r15 + offs
+ r16 = offs;
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
flags = r18;
__asm__ __volatile__ ("mfxer 18");
xer = r18;
- rA = r15;
/* Restore flags */
r18 = tmpcr;
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
- printf("%s %08x, %d => %08x (%08x %08x)\n",
- name, iargs[i], /*&iargs_priv[0], */ j, iargs_priv[i], /*rA, */ flags, xer);
+ printf("%s %08x, %d => %08x, %d (%08x %08x)\n",
+ name, iargs[i], offs, iargs_priv[i], r15-base, flags, xer);
}
free(iargs_priv);
}
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
flags = r18;
res = f17;
ur = *(uint64_t *)(&res);
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
as vex's accuracy isn't perfect */
ur &= 0xFFFFFFFFFFFFFF00ULL;
-#if defined TEST_FLOAT_FLAGS
- printf("%s %016llx, %016llx, %016llx => %016llx (%08x)\n",
- name, u0, u1, u2, ur, flags);
-#else
- printf("%s %016llx, %016llx, %016llx => %016llx\n",
+ printf("%s %016llx, %016llx, %016llx => %016llx",
name, u0, u1, u2, ur);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x)", flags);
#endif
+ printf("\n");
}
if (verbose) printf("\n");
}
u1 = *(uint64_t *)(&fargs[j]);
f14 = fargs[i];
f15 = fargs[j];
+
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
flags = r18;
res = f17;
ur = *(uint64_t *)(&res);
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
-#if defined TEST_FLOAT_FLAGS
- printf("%s %016llx, %016llx => %016llx (%08x)\n",
- name, u0, u1, ur, flags);
-#else
- printf("%s %016llx, %016llx => %016llx\n",
+
+ printf("%s %016llx, %016llx => %016llx",
name, u0, u1, ur);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x)", flags);
#endif
+ printf("\n");
}
if (verbose) printf("\n");
}
/* if we're testing fctiw or fctiwz, zap the hi 32bits,
as they're undefined */
- zap_hi_32bits = strstr(name,"fctiw") != NULL;
+ zap_hi_32bits = strstr(name, "fctiw") != NULL;
for (i=0; i<nb_fargs; i++) {
u0 = *(uint64_t *)(&fargs[i]);
f14 = fargs[i];
+
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
flags = r18;
res = f17;
ur = *(uint64_t *)(&res);
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
if (zap_hi_32bits)
ur &= 0xFFFFFFFFULL;
+ printf("%s %016llx => %016llx",
+ name, u0, ur);
#if defined TEST_FLOAT_FLAGS
- printf("%s %016llx => %016llx (%08x)\n", name, u0, ur, flags);
-#else
- printf("%s %016llx => %016llx\n", name, u0, ur);
+ printf(" (%08x)", flags);
#endif
+ printf("\n");
}
}
base = (HWord_t)&fargs[0];
}
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
patch_op_imm16(&func_buf[0], offs);
// load from fargs[idx] => r14 + offs
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
-#if defined TEST_FLOAT_FLAGS
- printf("%s %016llx, %4d => %016llx, %08x (%08x %08x)\n",
+ printf("%s %016llx, %4d => %016llx, %4d",
name, double_to_bits(src), offs,
- double_to_bits(res), r14, flags, xer);
-#else
- printf("%s %016llx, %4d => %016llx, %08x\n",
- name, double_to_bits(src), offs,
- double_to_bits(res), r14);
+ double_to_bits(res), r14-base);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x %08x)", flags, xer);
#endif
+ printf("\n");
}
if (verbose) printf("\n");
}
volatile HWord_t base;
volatile uint32_t flags, xer, tmpcr, tmpxer;
volatile double src, res;
- int i;
+ int i, offs;
/* offset within [1-nb_fargs:nb_fargs] */
for (i=1-nb_fargs; i<nb_fargs; i++) {
- r15 = i * 8; // offset = i * sizeof(double)
+ offs = i * 8; // offset = i * sizeof(double)
if (i < 0) { // base reg = start of array
src = fargs[nb_fargs-1 + i];
base = (HWord_t)&fargs[nb_fargs-1];
}
r14 = base;
+ r15 = offs;
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+ printf("%s %016llx, %4d => %016llx, %4d",
+ name, double_to_bits(src), r15/*offs*/,
+ double_to_bits(res), r14-base);
#if defined TEST_FLOAT_FLAGS
- printf("%s %016llx, %4d => %016llx, %08x (%08x %08x)\n",
- name, double_to_bits(src), r15,
- double_to_bits(res), r14, flags, xer);
-#else
- printf("%s %016llx, %4d => %016llx, %08x\n",
- name, double_to_bits(src), r15,
- double_to_bits(res), r14);
+ printf(" (%08x %08x)", flags, xer);
#endif
+ printf("\n");
}
}
}
*p_dst = 0; // clear dst
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
patch_op_imm16(&func_buf[0], offs);
// read from fargs[idx] => f14
f14 = src;
r15 = base;
- /* Save flags */
+ /* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
-#if defined TEST_FLOAT_FLAGS
- printf("%s %016llx, %4d => %016llx, %08x (%08x %08x)\n",
+ printf("%s %016llx, %4d => %016llx, %4d",
name, double_to_bits(src), offs,
- double_to_bits(*p_dst), r15, flags, xer);
-#else
- printf("%s %016llx, %4d => %016llx, %08x\n",
- name, double_to_bits(src), offs,
- double_to_bits(*p_dst), r15);
+ double_to_bits(*p_dst), r15-base);
+#if defined TEST_FLOAT_FLAGS
+ printf(" (%08x %08x)", flags, xer);
#endif
+ printf("\n");
}
free(fargs_priv);
}
double *fargs_priv;
int nb_tmp_fargs = nb_fargs;
+
/* if we're storing an fp single-precision, don't want nans
- the vex implementation doesn't like them (yet)
Note: This is actually a bigger problem: the vex implementation
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
- /* Set up flags for test */
+ /* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
__asm__ __volatile__ ("mtxer 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+ printf("%s %016llx, %4d => %016llx, %4d",
+ name, double_to_bits(src), r16/*offs*/,
+ double_to_bits(*p_dst), r15-base);
#if defined TEST_FLOAT_FLAGS
- printf("%s %016llx, %4d => %016llx, %08x (%08x %08x)\n",
- name, double_to_bits(src), offs,
- double_to_bits(*p_dst), r15, flags, xer);
-#else
- printf("%s %016llx, %4d => %016llx, %08x\n",
- name, double_to_bits(src), offs,
- double_to_bits(*p_dst), r15);
+ printf(" (%08x %08x)", flags, xer);
#endif
+ printf("\n");
#if 0
src = (unsigned int*)&vec_in;
dst = (unsigned int*)&vec_out;
+
printf("%s: %08x %08x %08x %08x\n", name,
src[0], src[1], src[2], src[3]);
printf("%s: => %08x %08x %08x %08x ", name,
src1 = (unsigned int*)&vec_in1;
src2 = (unsigned int*)&vec_in2;
dst = (unsigned int*)&vec_out;
+
printf("%s: ", name);
printf("%08x%08x%08x%08x, ", src1[0], src1[1], src1[2], src1[3]);
printf("%08x%08x%08x%08x\n", src2[0], src2[1], src2[2], src2[3]);
src2 = (unsigned int*)&vec_in2;
src3 = (unsigned int*)&vec_in3;
dst = (unsigned int*)&vec_out;
+
printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x, %08x%08x%08x%08x\n", name,
src1[0], src1[1], src1[2], src1[3],
src2[0], src2[1], src2[2], src2[3],
src1 = (unsigned int*)&vec_in1;
src2 = (unsigned int*)&vec_shft;
dst = (unsigned int*)&vec_out;
+
printf("%s: ", name);
printf("%08x%08x%08x%08x, ", src1[0], src1[1], src1[2], src1[3]);
printf("%08x%08x%08x%08x\n", src2[0], src2[1], src2[2], src2[3]);
for (j=0; j<16; j+=3) {
vec_out = (vector unsigned int){ 0,0,0,0 };
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
patch_op_imm(&func_buf[0], j, 16, 5);
/* Save flags */
src1 = (unsigned int*)&vec_in1;
dst = (unsigned int*)&vec_out;
+
printf("%s: ", name);
printf("%08x %08x %08x %08x, %u\n", src1[0], src1[1], src1[2], src1[3], j);
for (i=0; i<32; i++) {
vec_out = (vector unsigned int){ 0,0,0,0 };
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
patch_op_imm(&func_buf[0], i, 16, 5);
/* Save flags */
__asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
dst = (unsigned int*)&vec_out;
- printf("%s: %2d => ", name, i);
+ printf("%s: %2d => ", name, i);
printf("%08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
#if defined TEST_VSCR_SAT
p_vscr = (unsigned int*)𝓋
for (k=0; k<16; k+=14) {
vec_out = (vector unsigned int){ 0,0,0,0 };
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
patch_op_imm(&func_buf[0], k, 6, 4);
/* Save flags */
src1 = (unsigned int*)&vec_in1;
src2 = (unsigned int*)&vec_in2;
dst = (unsigned int*)&vec_out;
+
printf("%s: ", name);
printf("%08x%08x%08x%08x, %08x%08x%08x%08x, %u\n",
src1[0], src1[1], src1[2], src1[3],
__asm__ __volatile__ ("mtvscr %0" : : "vr" (tmpvscr));
dst = (unsigned int*)&vec_out;
+
printf("%s %3d, %3d", name, i, 0);
printf(" => %08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
printf("(%08x)\n", flags);
vec_out = (vector unsigned int)viargs_priv[i];
src = (unsigned int*)&vec_in;
dst = (unsigned int*)&vec_out;
+
printf("%s %3d, %08x %08x %08x %08x", name, j, src[0], src[1], src[2], src[3]);
printf(" => %08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
printf("(%08x)\n", flags);
src = (unsigned int*)&vec_in;
dst = (unsigned int*)&vec_out;
+
printf("%s: %08x %08x %08x %08x\n", name,
src[0], src[1], src[2], src[3]);
-
printf("%s: => %08x %08x %08x %08x ", name,
dst[0] & mask, dst[1] & mask, dst[2] & mask, dst[3] & mask);
#if defined TEST_VSCR_SAT
src1 = (unsigned int*)&vec_in1;
src2 = (unsigned int*)&vec_in2;
dst = (unsigned int*)&vec_out;
+
printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x\n", name,
src1[0], src1[1], src1[2], src1[3],
src2[0], src2[1], src2[2], src2[3]);
-
printf("%s: => %08x %08x %08x %08x ", name,
dst[0], dst[1], dst[2], dst[3]);
#if defined TEST_VSCR_SAT
src2 = (unsigned int*)&vec_in2;
src3 = (unsigned int*)&vec_in3;
dst = (unsigned int*)&vec_out;
+
printf("%s: %08x%08x%08x%08x, %08x%08x%08x%08x, %08x%08x%08x%08x\n", name,
src1[0], src1[1], src1[2], src1[3],
src2[0], src2[1], src2[2], src2[3],
src3[0], src3[1], src3[2], src3[3]);
-
printf("%s: => %08x %08x %08x %08x ", name,
dst[0], dst[1], dst[2], dst[3]);
#if defined TEST_VSCR_SAT
for (j=0; j<32; j+=9) {
vec_out = (vector unsigned int){ 0,0,0,0 };
- init_function( &func, func_buf );
/* Patch up the instruction */
+ init_function( &func, func_buf );
patch_op_imm(&func_buf[0], j, 16, 5);
/* Save flags */
src = (unsigned int*)&vec_in;
dst = (unsigned int*)&vec_out;
+
printf("%s: %08x (%13e), %2u", name, src[0], *(float*)(&src[0]), j);
printf(" => %08x (%13e) ", dst[0], *(float*)(&dst[0]));
// printf(" => %08x ", dst[0]);
* are in the same register
*/
r17 = iargs[k];
+
/* Save flags */
__asm__ __volatile__ ("mfcr 18");
tmpcr = r18;
__asm__ __volatile__ ("mfxer 18");
tmpxer = r18;
+
/* Set up flags for test */
r18 = 0;
__asm__ __volatile__ ("mtcr 18");
__asm__ __volatile__ ("mfxer 18");
xer = r18;
res = r17;
+
/* Restore flags */
r18 = tmpcr;
__asm__ __volatile__ ("mtcr 18");
r18 = tmpxer;
__asm__ __volatile__ ("mtxer 18");
+
printf("%s %08x, %08x, %08x => %08x (%08x %08x)\n",
name, iargs[i], iargs[j], iargs[k], res, flags, xer);
}
"\t-v: verbose (-v -v for more)\n"
"\t-h: print this help\n"
);
-#else
+#else // #if !defined (USAGE_SIMPLE)
fprintf(stderr,
"Usage: jm-insns [OPTION]\n"
"\t-i: test integer instructions (default)\n"
"\t-v: be verbose\n"
"\t-h: display this help and exit\n"
);
-#endif
+#endif // #if !defined (USAGE_SIMPLE)
}
+
int main (int argc, char **argv)
{
#if !defined (USAGE_SIMPLE)
if (flags.cr == -1)
flags.cr = 2; // both
-#else
+#else // #if !defined (USAGE_SIMPLE)
////////////////////////////////////////////////////////////////////////
/* Simple usage:
./jm-insns -i => int insns
}
arg_list_size = 0;
-#endif
+#endif // #if !defined (USAGE_SIMPLE)
build_iargs_table();
nego. ffffffff => 00000001 (40000000 00000000)
PPC logical insns with special forms:
- rlwimi 00000000, 0, 0, 0 => 00000001 (00000000 00000000)
+ rlwimi 00000000, 0, 0, 0 => 00000000 (00000000 00000000)
rlwimi 00000000, 0, 0, 31 => 00000000 (00000000 00000000)
rlwimi 00000000, 0, 31, 0 => 00000000 (00000000 00000000)
rlwimi 00000000, 0, 31, 31 => 00000000 (00000000 00000000)
PPC logical insns with special forms with flags update:
- rlwimi. 00000000, 0, 0, 0 => 7fffffff (40000000 00000000)
+ rlwimi. 00000000, 0, 0, 0 => 00000000 (20000000 00000000)
rlwimi. 00000000, 0, 0, 31 => 00000000 (20000000 00000000)
rlwimi. 00000000, 0, 31, 0 => 00000000 (20000000 00000000)
rlwimi. 00000000, 0, 31, 31 => 00000000 (20000000 00000000)
PPC integer load insns
with one register + one 16 bits immediate args with flags update:
- lbz 0, (00000000) => 00000000 (00000000 00000000)
- lbz 4, (000f423f) => 00000000 (00000000 00000000)
- lbz 8, (ffffffff) => 000000ff (00000000 00000000)
- lbz -8, (00000000) => 00000000 (00000000 00000000)
- lbz -4, (000f423f) => 00000000 (00000000 00000000)
- lbz 0, (ffffffff) => 000000ff (00000000 00000000)
-
- lbzu 0, (00000000) => 00000000 (00000000 00000000)
- lbzu 4, (000f423f) => 00000000 (00000000 00000000)
- lbzu 8, (ffffffff) => 000000ff (00000000 00000000)
- lbzu -8, (00000000) => 00000000 (00000000 00000000)
- lbzu -4, (000f423f) => 00000000 (00000000 00000000)
- lbzu 0, (ffffffff) => 000000ff (00000000 00000000)
-
- lha 0, (00000000) => 00000000 (00000000 00000000)
- lha 4, (000f423f) => 0000000f (00000000 00000000)
- lha 8, (ffffffff) => ffffffff (00000000 00000000)
- lha -8, (00000000) => 00000000 (00000000 00000000)
- lha -4, (000f423f) => 0000000f (00000000 00000000)
- lha 0, (ffffffff) => ffffffff (00000000 00000000)
-
- lhau 0, (00000000) => 00000000 (00000000 00000000)
- lhau 4, (000f423f) => 0000000f (00000000 00000000)
- lhau 8, (ffffffff) => ffffffff (00000000 00000000)
- lhau -8, (00000000) => 00000000 (00000000 00000000)
- lhau -4, (000f423f) => 0000000f (00000000 00000000)
- lhau 0, (ffffffff) => ffffffff (00000000 00000000)
-
- lhz 0, (00000000) => 00000000 (00000000 00000000)
- lhz 4, (000f423f) => 0000000f (00000000 00000000)
- lhz 8, (ffffffff) => 0000ffff (00000000 00000000)
- lhz -8, (00000000) => 00000000 (00000000 00000000)
- lhz -4, (000f423f) => 0000000f (00000000 00000000)
- lhz 0, (ffffffff) => 0000ffff (00000000 00000000)
-
- lhzu 0, (00000000) => 00000000 (00000000 00000000)
- lhzu 4, (000f423f) => 0000000f (00000000 00000000)
- lhzu 8, (ffffffff) => 0000ffff (00000000 00000000)
- lhzu -8, (00000000) => 00000000 (00000000 00000000)
- lhzu -4, (000f423f) => 0000000f (00000000 00000000)
- lhzu 0, (ffffffff) => 0000ffff (00000000 00000000)
-
- lwz 0, (00000000) => 00000000 (00000000 00000000)
- lwz 4, (000f423f) => 000f423f (00000000 00000000)
- lwz 8, (ffffffff) => ffffffff (00000000 00000000)
- lwz -8, (00000000) => 00000000 (00000000 00000000)
- lwz -4, (000f423f) => 000f423f (00000000 00000000)
- lwz 0, (ffffffff) => ffffffff (00000000 00000000)
-
- lwzu 0, (00000000) => 00000000 (00000000 00000000)
- lwzu 4, (000f423f) => 000f423f (00000000 00000000)
- lwzu 8, (ffffffff) => ffffffff (00000000 00000000)
- lwzu -8, (00000000) => 00000000 (00000000 00000000)
- lwzu -4, (000f423f) => 000f423f (00000000 00000000)
- lwzu 0, (ffffffff) => ffffffff (00000000 00000000)
+ lbz 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lbz 4, (000f423f) => 00000000, 0 (00000000 00000000)
+ lbz 8, (ffffffff) => 000000ff, 0 (00000000 00000000)
+ lbz -8, (00000000) => 00000000, 0 (00000000 00000000)
+ lbz -4, (000f423f) => 00000000, 0 (00000000 00000000)
+ lbz 0, (ffffffff) => 000000ff, 0 (00000000 00000000)
+
+ lbzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lbzu 4, (000f423f) => 00000000, 4 (00000000 00000000)
+ lbzu 8, (ffffffff) => 000000ff, 8 (00000000 00000000)
+ lbzu -8, (00000000) => 00000000, -8 (00000000 00000000)
+ lbzu -4, (000f423f) => 00000000, -4 (00000000 00000000)
+ lbzu 0, (ffffffff) => 000000ff, 0 (00000000 00000000)
+
+ lha 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lha 4, (000f423f) => 0000000f, 0 (00000000 00000000)
+ lha 8, (ffffffff) => ffffffff, 0 (00000000 00000000)
+ lha -8, (00000000) => 00000000, 0 (00000000 00000000)
+ lha -4, (000f423f) => 0000000f, 0 (00000000 00000000)
+ lha 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
+
+ lhau 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lhau 4, (000f423f) => 0000000f, 4 (00000000 00000000)
+ lhau 8, (ffffffff) => ffffffff, 8 (00000000 00000000)
+ lhau -8, (00000000) => 00000000, -8 (00000000 00000000)
+ lhau -4, (000f423f) => 0000000f, -4 (00000000 00000000)
+ lhau 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
+
+ lhz 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lhz 4, (000f423f) => 0000000f, 0 (00000000 00000000)
+ lhz 8, (ffffffff) => 0000ffff, 0 (00000000 00000000)
+ lhz -8, (00000000) => 00000000, 0 (00000000 00000000)
+ lhz -4, (000f423f) => 0000000f, 0 (00000000 00000000)
+ lhz 0, (ffffffff) => 0000ffff, 0 (00000000 00000000)
+
+ lhzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lhzu 4, (000f423f) => 0000000f, 4 (00000000 00000000)
+ lhzu 8, (ffffffff) => 0000ffff, 8 (00000000 00000000)
+ lhzu -8, (00000000) => 00000000, -8 (00000000 00000000)
+ lhzu -4, (000f423f) => 0000000f, -4 (00000000 00000000)
+ lhzu 0, (ffffffff) => 0000ffff, 0 (00000000 00000000)
+
+ lwz 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lwz 4, (000f423f) => 000f423f, 0 (00000000 00000000)
+ lwz 8, (ffffffff) => ffffffff, 0 (00000000 00000000)
+ lwz -8, (00000000) => 00000000, 0 (00000000 00000000)
+ lwz -4, (000f423f) => 000f423f, 0 (00000000 00000000)
+ lwz 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
+
+ lwzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+ lwzu 4, (000f423f) => 000f423f, 4 (00000000 00000000)
+ lwzu 8, (ffffffff) => ffffffff, 8 (00000000 00000000)
+ lwzu -8, (00000000) => 00000000, -8 (00000000 00000000)
+ lwzu -4, (000f423f) => 000f423f, -4 (00000000 00000000)
+ lwzu 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
PPC integer load insns with two register args:
- lbzx 0 (00000000) => 00000000 (00000000 00000000)
- lbzx 4 (000f423f) => 00000000 (00000000 00000000)
- lbzx 8 (ffffffff) => 000000ff (00000000 00000000)
+ lbzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lbzx 4 (000f423f) => 00000000, 0 (00000000 00000000)
+ lbzx 8 (ffffffff) => 000000ff, 0 (00000000 00000000)
- lbzux 0 (00000000) => 00000000 (00000000 00000000)
- lbzux 4 (000f423f) => 00000000 (00000000 00000000)
- lbzux 8 (ffffffff) => 000000ff (00000000 00000000)
+ lbzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lbzux 4 (000f423f) => 00000000, 4 (00000000 00000000)
+ lbzux 8 (ffffffff) => 000000ff, 8 (00000000 00000000)
- lhax 0 (00000000) => 00000000 (00000000 00000000)
- lhax 4 (000f423f) => 0000000f (00000000 00000000)
- lhax 8 (ffffffff) => ffffffff (00000000 00000000)
+ lhax 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhax 4 (000f423f) => 0000000f, 0 (00000000 00000000)
+ lhax 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
- lhaux 0 (00000000) => 00000000 (00000000 00000000)
- lhaux 4 (000f423f) => 0000000f (00000000 00000000)
- lhaux 8 (ffffffff) => ffffffff (00000000 00000000)
+ lhaux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhaux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
+ lhaux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
- lhzx 0 (00000000) => 00000000 (00000000 00000000)
- lhzx 4 (000f423f) => 0000000f (00000000 00000000)
- lhzx 8 (ffffffff) => 0000ffff (00000000 00000000)
+ lhzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhzx 4 (000f423f) => 0000000f, 0 (00000000 00000000)
+ lhzx 8 (ffffffff) => 0000ffff, 0 (00000000 00000000)
- lhzux 0 (00000000) => 00000000 (00000000 00000000)
- lhzux 4 (000f423f) => 0000000f (00000000 00000000)
- lhzux 8 (ffffffff) => 0000ffff (00000000 00000000)
+ lhzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lhzux 4 (000f423f) => 0000000f, 4 (00000000 00000000)
+ lhzux 8 (ffffffff) => 0000ffff, 8 (00000000 00000000)
- lwzx 0 (00000000) => 00000000 (00000000 00000000)
- lwzx 4 (000f423f) => 000f423f (00000000 00000000)
- lwzx 8 (ffffffff) => ffffffff (00000000 00000000)
+ lwzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lwzx 4 (000f423f) => 000f423f, 0 (00000000 00000000)
+ lwzx 8 (ffffffff) => ffffffff, 0 (00000000 00000000)
- lwzux 0 (00000000) => 00000000 (00000000 00000000)
- lwzux 4 (000f423f) => 000f423f (00000000 00000000)
- lwzux 8 (ffffffff) => ffffffff (00000000 00000000)
+ lwzux 0 (00000000) => 00000000, 0 (00000000 00000000)
+ lwzux 4 (000f423f) => 000f423f, 4 (00000000 00000000)
+ lwzux 8 (ffffffff) => ffffffff, 8 (00000000 00000000)
PPC integer store insns
with one register + one 16 bits immediate args with flags update:
- stb 00000000, 0 => 00000000 (00000000 00000000)
- stb 000f423f, 4 => 3f000000 (00000000 00000000)
- stb ffffffff, 8 => ff000000 (00000000 00000000)
- stb 00000000, -8 => 00000000 (00000000 00000000)
- stb 000f423f, -4 => 3f000000 (00000000 00000000)
- stb ffffffff, 0 => ff000000 (00000000 00000000)
-
- stbu 00000000, 0 => 00000000 (00000000 00000000)
- stbu 000f423f, 4 => 3f000000 (00000000 00000000)
- stbu ffffffff, 8 => ff000000 (00000000 00000000)
- stbu 00000000, -8 => 00000000 (00000000 00000000)
- stbu 000f423f, -4 => 3f000000 (00000000 00000000)
- stbu ffffffff, 0 => ff000000 (00000000 00000000)
-
- sth 00000000, 0 => 00000000 (00000000 00000000)
- sth 000f423f, 4 => 423f0000 (00000000 00000000)
- sth ffffffff, 8 => ffff0000 (00000000 00000000)
- sth 00000000, -8 => 00000000 (00000000 00000000)
- sth 000f423f, -4 => 423f0000 (00000000 00000000)
- sth ffffffff, 0 => ffff0000 (00000000 00000000)
-
- sthu 00000000, 0 => 00000000 (00000000 00000000)
- sthu 000f423f, 4 => 423f0000 (00000000 00000000)
- sthu ffffffff, 8 => ffff0000 (00000000 00000000)
- sthu 00000000, -8 => 00000000 (00000000 00000000)
- sthu 000f423f, -4 => 423f0000 (00000000 00000000)
- sthu ffffffff, 0 => ffff0000 (00000000 00000000)
-
- stw 00000000, 0 => 00000000 (00000000 00000000)
- stw 000f423f, 4 => 000f423f (00000000 00000000)
- stw ffffffff, 8 => ffffffff (00000000 00000000)
- stw 00000000, -8 => 00000000 (00000000 00000000)
- stw 000f423f, -4 => 000f423f (00000000 00000000)
- stw ffffffff, 0 => ffffffff (00000000 00000000)
-
- stwu 00000000, 0 => 00000000 (00000000 00000000)
- stwu 000f423f, 4 => 000f423f (00000000 00000000)
- stwu ffffffff, 8 => ffffffff (00000000 00000000)
- stwu 00000000, -8 => 00000000 (00000000 00000000)
- stwu 000f423f, -4 => 000f423f (00000000 00000000)
- stwu ffffffff, 0 => ffffffff (00000000 00000000)
+ stb 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stb 000f423f, 4 => 3f000000, 0 (00000000 00000000)
+ stb ffffffff, 8 => ff000000, 0 (00000000 00000000)
+ stb 00000000, -8 => 00000000, 0 (00000000 00000000)
+ stb 000f423f, -4 => 3f000000, 0 (00000000 00000000)
+ stb ffffffff, 0 => ff000000, 0 (00000000 00000000)
+
+ stbu 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stbu 000f423f, 4 => 3f000000, 4 (00000000 00000000)
+ stbu ffffffff, 8 => ff000000, 8 (00000000 00000000)
+ stbu 00000000, -8 => 00000000, -8 (00000000 00000000)
+ stbu 000f423f, -4 => 3f000000, -4 (00000000 00000000)
+ stbu ffffffff, 0 => ff000000, 0 (00000000 00000000)
+
+ sth 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sth 000f423f, 4 => 423f0000, 0 (00000000 00000000)
+ sth ffffffff, 8 => ffff0000, 0 (00000000 00000000)
+ sth 00000000, -8 => 00000000, 0 (00000000 00000000)
+ sth 000f423f, -4 => 423f0000, 0 (00000000 00000000)
+ sth ffffffff, 0 => ffff0000, 0 (00000000 00000000)
+
+ sthu 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sthu 000f423f, 4 => 423f0000, 4 (00000000 00000000)
+ sthu ffffffff, 8 => ffff0000, 8 (00000000 00000000)
+ sthu 00000000, -8 => 00000000, -8 (00000000 00000000)
+ sthu 000f423f, -4 => 423f0000, -4 (00000000 00000000)
+ sthu ffffffff, 0 => ffff0000, 0 (00000000 00000000)
+
+ stw 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stw 000f423f, 4 => 000f423f, 0 (00000000 00000000)
+ stw ffffffff, 8 => ffffffff, 0 (00000000 00000000)
+ stw 00000000, -8 => 00000000, 0 (00000000 00000000)
+ stw 000f423f, -4 => 000f423f, 0 (00000000 00000000)
+ stw ffffffff, 0 => ffffffff, 0 (00000000 00000000)
+
+ stwu 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stwu 000f423f, 4 => 000f423f, 4 (00000000 00000000)
+ stwu ffffffff, 8 => ffffffff, 8 (00000000 00000000)
+ stwu 00000000, -8 => 00000000, -8 (00000000 00000000)
+ stwu 000f423f, -4 => 000f423f, -4 (00000000 00000000)
+ stwu ffffffff, 0 => ffffffff, 0 (00000000 00000000)
PPC integer store insns with three register args:
- stbx 00000000, 0 => 00000000 (00000000 00000000)
- stbx 000f423f, 4 => 3f000000 (00000000 00000000)
- stbx ffffffff, 8 => ff000000 (00000000 00000000)
+ stbx 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stbx 000f423f, 4 => 3f000000, 0 (00000000 00000000)
+ stbx ffffffff, 8 => ff000000, 0 (00000000 00000000)
- stbux 00000000, 0 => 00000000 (00000000 00000000)
- stbux 000f423f, 4 => 3f000000 (00000000 00000000)
- stbux ffffffff, 8 => ff000000 (00000000 00000000)
+ stbux 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stbux 000f423f, 4 => 3f000000, 4 (00000000 00000000)
+ stbux ffffffff, 8 => ff000000, 8 (00000000 00000000)
- sthx 00000000, 0 => 00000000 (00000000 00000000)
- sthx 000f423f, 4 => 423f0000 (00000000 00000000)
- sthx ffffffff, 8 => ffff0000 (00000000 00000000)
+ sthx 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sthx 000f423f, 4 => 423f0000, 0 (00000000 00000000)
+ sthx ffffffff, 8 => ffff0000, 0 (00000000 00000000)
- sthux 00000000, 0 => 00000000 (00000000 00000000)
- sthux 000f423f, 4 => 423f0000 (00000000 00000000)
- sthux ffffffff, 8 => ffff0000 (00000000 00000000)
+ sthux 00000000, 0 => 00000000, 0 (00000000 00000000)
+ sthux 000f423f, 4 => 423f0000, 4 (00000000 00000000)
+ sthux ffffffff, 8 => ffff0000, 8 (00000000 00000000)
- stwx 00000000, 0 => 00000000 (00000000 00000000)
- stwx 000f423f, 4 => 000f423f (00000000 00000000)
- stwx ffffffff, 8 => ffffffff (00000000 00000000)
+ stwx 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stwx 000f423f, 4 => 000f423f, 0 (00000000 00000000)
+ stwx ffffffff, 8 => ffffffff, 0 (00000000 00000000)
- stwux 00000000, 0 => 00000000 (00000000 00000000)
- stwux 000f423f, 4 => 000f423f (00000000 00000000)
- stwux ffffffff, 8 => ffffffff (00000000 00000000)
+ stwux 00000000, 0 => 00000000, 0 (00000000 00000000)
+ stwux 000f423f, 4 => 000f423f, 4 (00000000 00000000)
+ stwux ffffffff, 8 => ffffffff, 8 (00000000 00000000)
All done. Tested 154 different instructions
projects / thirdparty / valgrind.git / commitdiff
