clk: renesas: r9a09g056: Add XSPI clock/reset

Add XSPI clock and reset entries.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250627204237.214635-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index 040acd4ae5dd3b934d01d9f0d5567c09f9a12c6d..437af86f49dd736c901c0e77ece26ebe0810550d 100644 (file)
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -39,6 +39,7 @@ enum clk_ids {
        CLK_SMUX2_XSPI_CLK0,
        CLK_SMUX2_XSPI_CLK1,
        CLK_PLLCM33_XSPI,
+       CLK_PLLCM33_GEAR,
        CLK_PLLCLN_DIV2,
        CLK_PLLCLN_DIV8,
        CLK_PLLCLN_DIV16,
@@ -123,6 +124,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
        DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1),
        DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3,
                  dtable_2_16),
+       DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64),
 
        DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
        DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
@@ -162,6 +164,8 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
                  CLK_PLLETH_DIV_125_FIX, 1, 1),
        DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G056_GBETH_1_CLK_PTP_REF_I,
                  CLK_PLLETH_DIV_125_FIX, 1, 1),
+       DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G056_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,
+                            FIXED_MOD_CONF_XSPI),
 };
 
 static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
@@ -219,6 +223,12 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
                                                BUS_MSTOP(1, BIT(7))),
        DEF_MOD("riic_7_ckm",                   CLK_PLLCLN_DIV16, 9, 11, 4, 27,
                                                BUS_MSTOP(1, BIT(8))),
+       DEF_MOD("spi_hclk",                     CLK_PLLCM33_GEAR, 9, 15, 4, 31,
+                                               BUS_MSTOP(4, BIT(5))),
+       DEF_MOD("spi_aclk",                     CLK_PLLCM33_GEAR, 10, 0, 5, 0,
+                                               BUS_MSTOP(4, BIT(5))),
+       DEF_MOD("spi_clk_spix2",                CLK_PLLCM33_XSPI, 10, 1, 5, 2,
+                                               BUS_MSTOP(4, BIT(5))),
        DEF_MOD("sdhi_0_imclk",                 CLK_PLLCLN_DIV8, 10, 3, 5, 3,
                                                BUS_MSTOP(8, BIT(2))),
        DEF_MOD("sdhi_0_imclk2",                CLK_PLLCLN_DIV8, 10, 4, 5, 4,
@@ -307,6 +317,8 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
        DEF_RST(9, 14, 4, 15),          /* RIIC_6_MRST */
        DEF_RST(9, 15, 4, 16),          /* RIIC_7_MRST */
        DEF_RST(10, 0, 4, 17),          /* RIIC_8_MRST */
+       DEF_RST(10, 3, 4, 20),          /* SPI_HRESETN */
+       DEF_RST(10, 4, 4, 21),          /* SPI_ARESETN */
        DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */
        DEF_RST(10, 8, 4, 25),          /* SDHI_1_IXRST */
        DEF_RST(10, 9, 4, 26),          /* SDHI_2_IXRST */

diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index ba4f0196643f31128d920b8ca3543fce68d105a2..840eed25aeda72f83644c6ba60d3f4368979b60e 100644 (file)
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -149,6 +149,8 @@ struct fixed_mod_conf {
                                 FIELD_PREP_CONST(BUS_MSTOP_BITS_MASK, (mask)))
 #define BUS_MSTOP_NONE         GENMASK(31, 0)
 
+#define FIXED_MOD_CONF_XSPI    FIXED_MOD_CONF_PACK(5, 1)
+
 /**
  * Definitions of CPG Core Clocks
  *