arm64: dts: qcom: sm8650: change labels to lower-case

DTS coding style expects labels to be lowercase.  No functional impact.
Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff).

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-14-0505bc7d2c56@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 3d8a807a81c9c15eeeaadf624a8e7f085b68ae9e..0c2b2a12663363b7d35eec89051697d69aba287d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -68,18 +68,18 @@
                #address-cells = <2>;
                #size-cells = <0>;
 
-               CPU0: cpu@0 {
+               cpu0: cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a520";
                        reg = <0 0>;
 
                        clocks = <&cpufreq_hw 0>;
 
-                       power-domains = <&CPU_PD0>;
+                       power-domains = <&cpu_pd0>;
                        power-domain-names = "psci";
 
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
 
@@ -87,13 +87,13 @@
 
                        #cooling-cells = <2>;
 
-                       L2_0: l2-cache {
+                       l2_0: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
                                cache-unified;
-                               next-level-cache = <&L3_0>;
+                               next-level-cache = <&l3_0>;
 
-                               L3_0: l3-cache {
+                               l3_0: l3-cache {
                                        compatible = "cache";
                                        cache-level = <3>;
                                        cache-unified;
@@ -101,18 +101,18 @@
                        };
                };
 
-               CPU1: cpu@100 {
+               cpu1: cpu@100 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a520";
                        reg = <0 0x100>;
 
                        clocks = <&cpufreq_hw 0>;
 
-                       power-domains = <&CPU_PD1>;
+                       power-domains = <&cpu_pd1>;
                        power-domain-names = "psci";
 
                        enable-method = "psci";
-                       next-level-cache = <&L2_0>;
+                       next-level-cache = <&l2_0>;
                        capacity-dmips-mhz = <1024>;
                        dynamic-power-coefficient = <100>;
 
@@ -121,18 +121,18 @@
                        #cooling-cells = <2>;
                };
 
-               CPU2: cpu@200 {
+               cpu2: cpu@200 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a720";
                        reg = <0 0x200>;
 
                        clocks = <&cpufreq_hw 3>;
 
-                       power-domains = <&CPU_PD2>;
+                       power-domains = <&cpu_pd2>;
                        power-domain-names = "psci";
 
                        enable-method = "psci";
-                       next-level-cache = <&L2_200>;
+                       next-level-cache = <&l2_200>;
                        capacity-dmips-mhz = <1792>;
                        dynamic-power-coefficient = <238>;
 
@@ -140,26 +140,26 @@
 
                        #cooling-cells = <2>;
 
-                       L2_200: l2-cache {
+                       l2_200: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
                                cache-unified;
-                               next-level-cache = <&L3_0>;
+                               next-level-cache = <&l3_0>;
                        };
                };
 
-               CPU3: cpu@300 {
+               cpu3: cpu@300 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a720";
                        reg = <0 0x300>;
 
                        clocks = <&cpufreq_hw 3>;
 
-                       power-domains = <&CPU_PD3>;
+                       power-domains = <&cpu_pd3>;
                        power-domain-names = "psci";
 
                        enable-method = "psci";
-                       next-level-cache = <&L2_200>;
+                       next-level-cache = <&l2_200>;
                        capacity-dmips-mhz = <1792>;
                        dynamic-power-coefficient = <238>;
 
@@ -168,18 +168,18 @@
                        #cooling-cells = <2>;
                };
 
-               CPU4: cpu@400 {
+               cpu4: cpu@400 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a720";
                        reg = <0 0x400>;
 
                        clocks = <&cpufreq_hw 3>;
 
-                       power-domains = <&CPU_PD4>;
+                       power-domains = <&cpu_pd4>;
                        power-domain-names = "psci";
 
                        enable-method = "psci";
-                       next-level-cache = <&L2_400>;
+                       next-level-cache = <&l2_400>;
                        capacity-dmips-mhz = <1792>;
                        dynamic-power-coefficient = <238>;
 
@@ -187,26 +187,26 @@
 
                        #cooling-cells = <2>;
 
-                       L2_400: l2-cache {
+                       l2_400: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
                                cache-unified;
-                               next-level-cache = <&L3_0>;
+                               next-level-cache = <&l3_0>;
                        };
                };
 
-               CPU5: cpu@500 {
+               cpu5: cpu@500 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a720";
                        reg = <0 0x500>;
 
                        clocks = <&cpufreq_hw 1>;
 
-                       power-domains = <&CPU_PD5>;
+                       power-domains = <&cpu_pd5>;
                        power-domain-names = "psci";
 
                        enable-method = "psci";
-                       next-level-cache = <&L2_500>;
+                       next-level-cache = <&l2_500>;
                        capacity-dmips-mhz = <1792>;
                        dynamic-power-coefficient = <238>;
 
@@ -214,26 +214,26 @@
 
                        #cooling-cells = <2>;
 
-                       L2_500: l2-cache {
+                       l2_500: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
                                cache-unified;
-                               next-level-cache = <&L3_0>;
+                               next-level-cache = <&l3_0>;
                        };
                };
 
-               CPU6: cpu@600 {
+               cpu6: cpu@600 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a720";
                        reg = <0 0x600>;
 
                        clocks = <&cpufreq_hw 1>;
 
-                       power-domains = <&CPU_PD6>;
+                       power-domains = <&cpu_pd6>;
                        power-domain-names = "psci";
 
                        enable-method = "psci";
-                       next-level-cache = <&L2_600>;
+                       next-level-cache = <&l2_600>;
                        capacity-dmips-mhz = <1792>;
                        dynamic-power-coefficient = <238>;
 
@@ -241,26 +241,26 @@
 
                        #cooling-cells = <2>;
 
-                       L2_600: l2-cache {
+                       l2_600: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
                                cache-unified;
-                               next-level-cache = <&L3_0>;
+                               next-level-cache = <&l3_0>;
                        };
                };
 
-               CPU7: cpu@700 {
+               cpu7: cpu@700 {
                        device_type = "cpu";
                        compatible = "arm,cortex-x4";
                        reg = <0 0x700>;
 
                        clocks = <&cpufreq_hw 2>;
 
-                       power-domains = <&CPU_PD7>;
+                       power-domains = <&cpu_pd7>;
                        power-domain-names = "psci";
 
                        enable-method = "psci";
-                       next-level-cache = <&L2_700>;
+                       next-level-cache = <&l2_700>;
                        capacity-dmips-mhz = <1894>;
                        dynamic-power-coefficient = <588>;
 
@@ -268,46 +268,46 @@
 
                        #cooling-cells = <2>;
 
-                       L2_700: l2-cache {
+                       l2_700: l2-cache {
                                compatible = "cache";
                                cache-level = <2>;
                                cache-unified;
-                               next-level-cache = <&L3_0>;
+                               next-level-cache = <&l3_0>;
                        };
                };
 
                cpu-map {
                        cluster0 {
                                core0 {
-                                       cpu = <&CPU0>;
+                                       cpu = <&cpu0>;
                                };
 
                                core1 {
-                                       cpu = <&CPU1>;
+                                       cpu = <&cpu1>;
                                };
 
                                core2 {
-                                       cpu = <&CPU2>;
+                                       cpu = <&cpu2>;
                                };
 
                                core3 {
-                                       cpu = <&CPU3>;
+                                       cpu = <&cpu3>;
                                };
 
                                core4 {
-                                       cpu = <&CPU4>;
+                                       cpu = <&cpu4>;
                                };
 
                                core5 {
-                                       cpu = <&CPU5>;
+                                       cpu = <&cpu5>;
                                };
 
                                core6 {
-                                       cpu = <&CPU6>;
+                                       cpu = <&cpu6>;
                                };
 
                                core7 {
-                                       cpu = <&CPU7>;
+                                       cpu = <&cpu7>;
                                };
                        };
                };
@@ -315,7 +315,7 @@
                idle-states {
                        entry-method = "psci";
 
-                       SILVER_CPU_SLEEP_0: cpu-sleep-0-0 {
+                       silver_cpu_sleep_0: cpu-sleep-0-0 {
                                compatible = "arm,idle-state";
                                idle-state-name = "silver-rail-power-collapse";
                                arm,psci-suspend-param = <0x40000004>;
@@ -325,7 +325,7 @@
                                local-timer-stop;
                        };
 
-                       GOLD_CPU_SLEEP_0: cpu-sleep-1-0 {
+                       gold_cpu_sleep_0: cpu-sleep-1-0 {
                                compatible = "arm,idle-state";
                                idle-state-name = "gold-rail-power-collapse";
                                arm,psci-suspend-param = <0x40000004>;
@@ -335,7 +335,7 @@
                                local-timer-stop;
                        };
 
-                       GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 {
+                       gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
                                compatible = "arm,idle-state";
                                idle-state-name = "gold-plus-rail-power-collapse";
                                arm,psci-suspend-param = <0x40000004>;
@@ -347,7 +347,7 @@
                };
 
                domain-idle-states {
-                       CLUSTER_SLEEP_0: cluster-sleep-0 {
+                       cluster_sleep_0: cluster-sleep-0 {
                                compatible = "domain-idle-state";
                                arm,psci-suspend-param = <0x41000044>;
                                entry-latency-us = <750>;
@@ -355,7 +355,7 @@
                                min-residency-us = <9144>;
                        };
 
-                       CLUSTER_SLEEP_1: cluster-sleep-1 {
+                       cluster_sleep_1: cluster-sleep-1 {
                                compatible = "domain-idle-state";
                                arm,psci-suspend-param = <0x4100c344>;
                                entry-latency-us = <2800>;
@@ -411,58 +411,58 @@
                compatible = "arm,psci-1.0";
                method = "smc";
 
-               CPU_PD0: power-domain-cpu0 {
+               cpu_pd0: power-domain-cpu0 {
                        #power-domain-cells = <0>;
-                       power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+                       power-domains = <&cluster_pd>;
+                       domain-idle-states = <&silver_cpu_sleep_0>;
                };
 
-               CPU_PD1: power-domain-cpu1 {
+               cpu_pd1: power-domain-cpu1 {
                        #power-domain-cells = <0>;
-                       power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+                       power-domains = <&cluster_pd>;
+                       domain-idle-states = <&silver_cpu_sleep_0>;
                };
 
-               CPU_PD2: power-domain-cpu2 {
+               cpu_pd2: power-domain-cpu2 {
                        #power-domain-cells = <0>;
-                       power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&SILVER_CPU_SLEEP_0>;
+                       power-domains = <&cluster_pd>;
+                       domain-idle-states = <&silver_cpu_sleep_0>;
                };
 
-               CPU_PD3: power-domain-cpu3 {
+               cpu_pd3: power-domain-cpu3 {
                        #power-domain-cells = <0>;
-                       power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+                       power-domains = <&cluster_pd>;
+                       domain-idle-states = <&gold_cpu_sleep_0>;
                };
 
-               CPU_PD4: power-domain-cpu4 {
+               cpu_pd4: power-domain-cpu4 {
                        #power-domain-cells = <0>;
-                       power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+                       power-domains = <&cluster_pd>;
+                       domain-idle-states = <&gold_cpu_sleep_0>;
                };
 
-               CPU_PD5: power-domain-cpu5 {
+               cpu_pd5: power-domain-cpu5 {
                        #power-domain-cells = <0>;
-                       power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+                       power-domains = <&cluster_pd>;
+                       domain-idle-states = <&gold_cpu_sleep_0>;
                };
 
-               CPU_PD6: power-domain-cpu6 {
+               cpu_pd6: power-domain-cpu6 {
                        #power-domain-cells = <0>;
-                       power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&GOLD_CPU_SLEEP_0>;
+                       power-domains = <&cluster_pd>;
+                       domain-idle-states = <&gold_cpu_sleep_0>;
                };
 
-               CPU_PD7: power-domain-cpu7 {
+               cpu_pd7: power-domain-cpu7 {
                        #power-domain-cells = <0>;
-                       power-domains = <&CLUSTER_PD>;
-                       domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>;
+                       power-domains = <&cluster_pd>;
+                       domain-idle-states = <&gold_plus_cpu_sleep_0>;
                };
 
-               CLUSTER_PD: power-domain-cluster {
+               cluster_pd: power-domain-cluster {
                        #power-domain-cells = <0>;
-                       domain-idle-states = <&CLUSTER_SLEEP_0>,
-                                            <&CLUSTER_SLEEP_1>;
+                       domain-idle-states = <&cluster_sleep_0>,
+                                            <&cluster_sleep_1>;
                };
        };
 
@@ -5081,7 +5081,7 @@
                                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 
-                       power-domains = <&CLUSTER_PD>;
+                       power-domains = <&cluster_pd>;
 
                        qcom,tcs-offset = <0xd00>;
                        qcom,drv-id = <2>;