net/mlx5: Fix 1600G link mode enum naming

Rename TAUI/TBASE to GAUI/GBASE in 1600G link mode identifier and its
usage in ethtool and link-info tables.

Reported-by: Dawid Osuchowski <dawid.osuchowski@linux.intel.com>
Signed-off-by: Yael Chemla <ychemla@nvidia.com>
Reviewed-by: Shahar Shitrit <shshitrit@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
Reviewed-by: Dawid Osuchowski <dawid.osuchowski@linux.intel.com>
Reported-by: Dawid Osuchowski <dawid.osuchowski@linux.intel.com>
Signed-off-by: Yael Chemla <ychemla@nvidia.com>
Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
Link: https://patch.msgid.link/20260204194324.1723534-1-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c
index 40284bbb45d6dcc8ea7aefa429a8ebfefcad1ac7..947faacd75bbd9824b237505d2a2f09070ccdb48 100644 (file)
--- a/drivers/infiniband/hw/mlx5/main.c
+++ b/drivers/infiniband/hw/mlx5/main.c
@@ -511,7 +511,7 @@ static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
                *active_width = IB_WIDTH_4X;
                *active_speed = IB_SPEED_XDR;
                break;
-       case MLX5E_PROT_MASK(MLX5E_1600TAUI_8_1600TBASE_CR8_KR8):
+       case MLX5E_PROT_MASK(MLX5E_1600GAUI_8_1600GBASE_CR8_KR8):
                *active_width = IB_WIDTH_8X;
                *active_speed = IB_SPEED_XDR;
                break;

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
index d3fef1e7e2f70599a5c31d3828223ade446c8ad5..4a8dc85d5924cf3ecac05cede09d9b581fcad0dd 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c
@@ -261,7 +261,7 @@ void mlx5e_build_ptys2ethtool_map(void)
                                       ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT,
                                       ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT,
                                       ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT);
-       MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1600TAUI_8_1600TBASE_CR8_KR8, ext,
+       MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1600GAUI_8_1600GBASE_CR8_KR8, ext,
                                       ETHTOOL_LINK_MODE_1600000baseCR8_Full_BIT,
                                       ETHTOOL_LINK_MODE_1600000baseKR8_Full_BIT,
                                       ETHTOOL_LINK_MODE_1600000baseDR8_Full_BIT,

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c
index 9fca591652f2dc4eaa93b5ce204a5b4517cffe54..ee8b9765c5bafd98b8ae14e6427f8cbf2e6c6082 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/port.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c
@@ -1111,7 +1111,7 @@ mlx5e_ext_link_info[MLX5E_EXT_LINK_MODES_NUMBER] = {
        [MLX5E_200GAUI_1_200GBASE_CR1_KR1]      = {.speed = 200000, .lanes = 1},
        [MLX5E_400GAUI_2_400GBASE_CR2_KR2]      = {.speed = 400000, .lanes = 2},
        [MLX5E_800GAUI_4_800GBASE_CR4_KR4]      = {.speed = 800000, .lanes = 4},
-       [MLX5E_1600TAUI_8_1600TBASE_CR8_KR8]    = {.speed = 1600000, .lanes = 8},
+       [MLX5E_1600GAUI_8_1600GBASE_CR8_KR8]    = {.speed = 1600000, .lanes = 8},
 };
 
 int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext,

diff --git a/include/linux/mlx5/port.h b/include/linux/mlx5/port.h
index 1df9d9a57bbc329a74bf129b2c5e7d701effb641..12d366b12e2ee2eab53de60fc7dedac8108220a0 100644 (file)
--- a/include/linux/mlx5/port.h
+++ b/include/linux/mlx5/port.h
@@ -112,7 +112,7 @@ enum mlx5e_ext_link_mode {
        MLX5E_400GAUI_2_400GBASE_CR2_KR2        = 17,
        MLX5E_800GAUI_8_800GBASE_CR8_KR8        = 19,
        MLX5E_800GAUI_4_800GBASE_CR4_KR4        = 20,
-       MLX5E_1600TAUI_8_1600TBASE_CR8_KR8      = 23,
+       MLX5E_1600GAUI_8_1600GBASE_CR8_KR8      = 23,
        MLX5E_EXT_LINK_MODES_NUMBER,
 };