drm/msm/dpu: stop passing mdss_ver to setup_timing_gen()

As a preparation to further MDSS-revision cleanups stop passing MDSS
revision to the setup_timing_gen() callback. Instead store a pointer to
it inside struct dpu_hw_intf and use it diretly. It's not that the MDSS
revision can chance between dpu_hw_intf_init() and
dpu_encoder_phys_vid_setup_timing_engine().

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/655362/
Link: https://lore.kernel.org/r/20250522-dpu-drop-features-v5-1-3b2085a07884@oss.qualcomm.com

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 1c468ca5d692b7fee0438427c5b94af491dba94f..939ab27775d8f9c9b0aa0399a1469c709b4bc219 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -313,8 +313,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
 
        spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
        phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf,
-                       &timing_params, fmt,
-                       phys_enc->dpu_kms->catalog->mdss_ver);
+                       &timing_params, fmt);
        phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
 
        /* setup which pp blk will connect to this intf */

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index fb1d25baa518057e74fec3406faffd48969d492b..1d56c21ac79095ab515aeb485346e1eb5793c260 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -98,8 +98,7 @@
 
 static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
                const struct dpu_hw_intf_timing_params *p,
-               const struct msm_format *fmt,
-               const struct dpu_mdss_version *mdss_ver)
+               const struct msm_format *fmt)
 {
        struct dpu_hw_blk_reg_map *c = &intf->hw;
        u32 hsync_period, vsync_period;
@@ -180,7 +179,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,
 
        /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */
        if (p->compression_en && !dp_intf &&
-           mdss_ver->core_major_ver >= 7)
+           intf->mdss_ver->core_major_ver >= 7)
                intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS;
 
        hsync_data_start_x = hsync_start_x;
@@ -580,6 +579,8 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,
        c->idx = cfg->id;
        c->cap = cfg;
 
+       c->mdss_ver = mdss_rev;
+
        c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine;
        c->ops.setup_prg_fetch  = dpu_hw_intf_setup_prg_fetch;
        c->ops.get_status = dpu_hw_intf_get_status;

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
index 114be272ac0ae67fe0d4dfc0c117baa4106f77c9..f31067a9aaf1d6b96c77157135122e5e8bccb7c4 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
@@ -81,8 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg {
 struct dpu_hw_intf_ops {
        void (*setup_timing_gen)(struct dpu_hw_intf *intf,
                        const struct dpu_hw_intf_timing_params *p,
-                       const struct msm_format *fmt,
-                       const struct dpu_mdss_version *mdss_ver);
+                       const struct msm_format *fmt);
 
        void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
                        const struct dpu_hw_intf_prog_fetch *fetch);
@@ -126,6 +125,8 @@ struct dpu_hw_intf {
        enum dpu_intf idx;
        const struct dpu_intf_cfg *cap;
 
+       const struct dpu_mdss_version *mdss_ver;
+
        /* ops */
        struct dpu_hw_intf_ops ops;
 };