media: i2c: ds90ub960: Add UB9702 specific registers

Add UB9702 specific registers which will be used in the following
patches.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Signed-off-by: Jai Luthra <jai.luthra@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>

diff --git a/drivers/media/i2c/ds90ub960.c b/drivers/media/i2c/ds90ub960.c
index f9af6d643ac86de22286b2107d747341c7d6f9b0..c56398aa895f05029879fb336bc52c932fee494d 100644 (file)
--- a/drivers/media/i2c/ds90ub960.c
+++ b/drivers/media/i2c/ds90ub960.c
@@ -391,12 +391,47 @@
 
 /* UB9702 Registers */
 
+#define UB9702_SR_CSI_EXCLUSIVE_FWD2           0x3c
 #define UB9702_SR_REFCLK_FREQ                  0x3d
+#define UB9702_RR_RX_CTL_1                     0x80
+#define UB9702_RR_RX_CTL_2                     0x87
 #define UB9702_RR_VC_ID_MAP(x)                 (0xa0 + (x))
 #define UB9702_SR_FPD_RATE_CFG                 0xc2
 #define UB9702_SR_CSI_PLL_DIV                  0xc9
+#define UB9702_RR_RX_SM_SEL_2                  0xd4
 #define UB9702_RR_CHANNEL_MODE                 0xe4
 
+#define UB9702_IND_TARGET_SAR_ADC              0x0a
+
+#define UB9702_IR_RX_ANA_FPD_BC_CTL0           0x04
+#define UB9702_IR_RX_ANA_FPD_BC_CTL1           0x0d
+#define UB9702_IR_RX_ANA_FPD_BC_CTL2           0x1b
+#define UB9702_IR_RX_ANA_SYSTEM_INIT_REG0      0x21
+#define UB9702_IR_RX_ANA_AEQ_ALP_SEL6          0x27
+#define UB9702_IR_RX_ANA_AEQ_ALP_SEL7          0x28
+#define UB9702_IR_RX_ANA_AEQ_ALP_SEL10         0x2b
+#define UB9702_IR_RX_ANA_AEQ_ALP_SEL11         0x2c
+#define UB9702_IR_RX_ANA_EQ_ADAPT_CTRL         0x2e
+#define UB9702_IR_RX_ANA_AEQ_CFG_1             0x34
+#define UB9702_IR_RX_ANA_AEQ_CFG_2             0x4d
+#define UB9702_IR_RX_ANA_GAIN_CTRL_0           0x71
+#define UB9702_IR_RX_ANA_GAIN_CTRL_0           0x71
+#define UB9702_IR_RX_ANA_VGA_CTRL_SEL_1                0x72
+#define UB9702_IR_RX_ANA_VGA_CTRL_SEL_2                0x73
+#define UB9702_IR_RX_ANA_VGA_CTRL_SEL_3                0x74
+#define UB9702_IR_RX_ANA_VGA_CTRL_SEL_6                0x77
+#define UB9702_IR_RX_ANA_AEQ_CFG_3             0x79
+#define UB9702_IR_RX_ANA_AEQ_CFG_4             0x85
+#define UB9702_IR_RX_ANA_EQ_CTRL_SEL_15                0x87
+#define UB9702_IR_RX_ANA_EQ_CTRL_SEL_24                0x90
+#define UB9702_IR_RX_ANA_EQ_CTRL_SEL_38                0x9e
+#define UB9702_IR_RX_ANA_FPD3_CDR_CTRL_SEL_5   0xa5
+#define UB9702_IR_RX_ANA_FPD3_AEQ_CTRL_SEL_1   0xa8
+#define UB9702_IR_RX_ANA_EQ_OVERRIDE_CTRL      0xf0
+#define UB9702_IR_RX_ANA_VGA_CTRL_SEL_8                0xf1
+
+#define UB9702_IR_CSI_ANA_CSIPLL_REG_1         0x92
+
 /* EQ related */
 
 #define UB960_MIN_AEQ_STROBE_POS -7