arm64: dts: corstone1000: Add definitions for secondary CPU cores

Add cpu{1-3} device nodes to the corstone1000 device tree to enable the
support for secondary CPU cores.

This update facilitates symmetric multiprocessing (SMP) support on the
corstone1000 Fixed Virtual Platform (FVP), allowing the secondary cores
to be properly initialised and utilised.

Only FVP platform will have SMP support and hence the secondary cpu
definitions are not added to corstone1000.dtsi.

Signed-off-by: Hugues KAMBA MPIANA <hugues.kambampiana@arm.com>
Message-Id: <20250303170012.469576-1-hugues.kambampiana@arm.com>
(sudeep.holla: Added psci enable-method for cpu0)
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
index abd01356299581e7bc8fb939856deb6a186479bc..66ba6b02719388003ddea774a39343ba77a5af44 100644 (file)
--- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
+++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
@@ -49,3 +49,29 @@
                clock-names = "smclk", "apb_pclk";
        };
 };
+
+&cpus {
+       cpu1: cpu@1 {
+               device_type = "cpu";
+               compatible = "arm,cortex-a35";
+               reg = <0x1>;
+               enable-method = "psci";
+               next-level-cache = <&L2_0>;
+       };
+
+       cpu2: cpu@2 {
+               device_type = "cpu";
+               compatible = "arm,cortex-a35";
+               reg = <0x2>;
+               enable-method = "psci";
+               next-level-cache = <&L2_0>;
+       };
+
+       cpu3: cpu@3 {
+               device_type = "cpu";
+               compatible = "arm,cortex-a35";
+               reg = <0x3>;
+               enable-method = "psci";
+               next-level-cache = <&L2_0>;
+       };
+};

diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index bb9b96fb531440c08258c268df39b491eed5a448..56ada8728b608a4ac9fe228ac0812fdeb0350578 100644 (file)
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -21,7 +21,7 @@
                stdout-path = "serial0:115200n8";
        };
 
-       cpus {
+       cpus: cpus {
                #address-cells = <1>;
                #size-cells = <0>;
 
@@ -29,6 +29,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a35";
                        reg = <0>;
+                       enable-method = "psci";
                        next-level-cache = <&L2_0>;
                };
        };