arm64: dts: apm/shadowcat: More clock clean-ups

A fixed-factor-clock only provides 1 clock, so "#clock-cells" must be 0.

The "snps,designware-i2c" node is not a clock provider, so drop
"#clock-cells.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251216-dt-apm-v1-1-0bf2bf8b982c@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index 5bbedb0a7107d5f5163c5b80d81f260c3f009838..032d37a321933352a2239f3492c51e09806548ce 100644 (file)
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -295,7 +295,7 @@
 
                        socplldiv2: socplldiv2  {
                                compatible = "fixed-factor-clock";
-                               #clock-cells = <1>;
+                               #clock-cells = <0>;
                                clocks = <&socpll 0>;
                                clock-mult = <1>;
                                clock-div = <2>;
@@ -305,7 +305,7 @@
                        ahbclk: ahbclk@17000000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x17000000 0x0 0x2000>;
                                reg-names = "div-reg";
                                divider-offset = <0x164>;
@@ -329,7 +329,7 @@
                        sdioclk: sdioclk@1f2ac000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f2ac000 0x0 0x1000
                                        0x0 0x17000000 0x0 0x2000>;
                                reg-names = "csr-reg", "div-reg";
@@ -346,7 +346,7 @@
                        pcie0clk: pcie0clk@1f2bc000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f2bc000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "pcie0clk";
@@ -355,7 +355,7 @@
                        pcie1clk: pcie1clk@1f2cc000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f2cc000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                clock-output-names = "pcie1clk";
@@ -364,7 +364,7 @@
                        xge0clk: xge0clk@1f61c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f61c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                enable-mask = <0x3>;
@@ -375,7 +375,7 @@
                        xge1clk: xge1clk@1f62c000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x1f62c000 0x0 0x1000>;
                                reg-names = "csr-reg";
                                enable-mask = <0x3>;
@@ -386,7 +386,7 @@
                        rngpkaclk: rngpkaclk@17000000 {
                                compatible = "apm,xgene-device-clock";
                                #clock-cells = <1>;
-                               clocks = <&socplldiv2 0>;
+                               clocks = <&socplldiv2>;
                                reg = <0x0 0x17000000 0x0 0x2000>;
                                reg-names = "csr-reg";
                                csr-offset = <0xc>;
@@ -799,7 +799,6 @@
                        compatible = "snps,designware-i2c";
                        reg = <0x0 0x10511000 0x0 0x1000>;
                        interrupts = <0 0x45 0x4>;
-                       #clock-cells = <1>;
                        clocks = <&sbapbclk 0>;
                };