arm64: tegra: Add pinctrl definitions for pcie-ep nodes

When the PCIe controller is running in endpoint mode, the controller
initialization is triggered by a PERST# (PCIe reset) GPIO deassertion.

The driver has configured an IRQ to trigger when the PERST# GPIO changes
state. Without the pinctrl definition, we do not get an IRQ when PERST#
is deasserted, so the PCIe controller never gets initialized.

Add the missing definitions, so that the controller actually gets
initialized.

Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
Fixes: 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition")
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
[treding@nvidia.com: add blank lines to separate blocks]
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index df034dbb82853ef23cbe03eeb4f4edee5583efbb..5657045c53d90dc3bc5f2741ea60d505ae30edd7 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/power/tegra234-powergate.h>
 #include <dt-bindings/reset/tegra234-reset.h>
 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 
 / {
        compatible = "nvidia,tegra234";
@@ -127,6 +128,56 @@
                pinmux: pinmux@2430000 {
                        compatible = "nvidia,tegra234-pinmux";
                        reg = <0x0 0x2430000 0x0 0x19100>;
+
+                       pex_rst_c4_in_state: pinmux-pex-rst-c4-in {
+                               pex_rst {
+                                       nvidia,pins = "pex_l4_rst_n_pl1";
+                                       nvidia,function = "rsvd1";
+                                       nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                       nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                       nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               };
+                       };
+
+                       pex_rst_c5_in_state: pinmux-pex-rst-c5-in {
+                               pex_rst {
+                                       nvidia,pins = "pex_l5_rst_n_paf1";
+                                       nvidia,function = "rsvd1";
+                                       nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                       nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                       nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               };
+                       };
+
+                       pex_rst_c6_in_state: pinmux-pex-rst-c6-in {
+                               pex_rst {
+                                       nvidia,pins = "pex_l6_rst_n_paf3";
+                                       nvidia,function = "rsvd1";
+                                       nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                       nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                       nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               };
+                       };
+
+                       pex_rst_c7_in_state: pinmux-pex-rst-c7-in {
+                               pex_rst {
+                                       nvidia,pins = "pex_l7_rst_n_pag1";
+                                       nvidia,function = "rsvd1";
+                                       nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                       nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                       nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               };
+                       };
+
+                       pex_rst_c10_in_state: pinmux-pex-rst-c10-in {
+                               pex_rst {
+                                       nvidia,pins = "pex_l10_rst_n_pag7";
+                                       nvidia,function = "rsvd1";
+                                       nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                       nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                       nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                               };
+                       };
                };
 
                gpcdma: dma-controller@2600000 {
@@ -4630,6 +4681,8 @@
                                 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
                        reset-names = "apb", "core";
 
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pex_rst_c10_in_state>;
                        interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
                        interrupt-names = "intr";
 
@@ -4881,6 +4934,8 @@
                               <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
                        reset-names = "apb", "core";
 
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pex_rst_c4_in_state>;
                        interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
                        interrupt-names = "intr";
                        nvidia,bpmp = <&bpmp 4>;
@@ -5023,6 +5078,8 @@
                                 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
                        reset-names = "apb", "core";
 
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pex_rst_c5_in_state>;
                        interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;  /* controller interrupt */
                        interrupt-names = "intr";
 
@@ -5115,6 +5172,8 @@
                                 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
                        reset-names = "apb", "core";
 
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pex_rst_c6_in_state>;
                        interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
                        interrupt-names = "intr";
 
@@ -5207,6 +5266,8 @@
                                 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
                        reset-names = "apb", "core";
 
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pex_rst_c7_in_state>;
                        interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
                        interrupt-names = "intr";