PowerPC64 (both big-endian and little-endian) supports efficient
unaligned memory access, similar to x86. This extends the existing
fast path that avoids byte-by-byte loads in the MD5 and MD4 SET/GET
macros.
On POWER8 ppc64le, this eliminates 3 shifts + 3 ORs per 32-bit word
load, replacing them with a single lwz (or lwbrx on big-endian).
Co Authored By Claude Opus 4.6 (1M context)
Closes #20985
* The check for little-endian architectures that tolerate unaligned memory
* accesses is an optimization. Nothing will break if it does not work.
*/
-#if defined(__i386__) || defined(__x86_64__) || defined(__vax__)
+#if defined(__i386__) || defined(__x86_64__) || \
+ defined(__vax__) || defined(__powerpc64__)
#define MD4_SET(n) (*(const uint32_t *)(const void *)&ptr[(n) * 4])
#define MD4_GET(n) MD4_SET(n)
#else
* The check for little-endian architectures that tolerate unaligned memory
* accesses is an optimization. Nothing will break if it does not work.
*/
-#if defined(__i386__) || defined(__x86_64__) || defined(__vax__)
+#if defined(__i386__) || defined(__x86_64__) || \
+ defined(__vax__) || defined(__powerpc64__)
#define MD5_SET(n) (*(const uint32_t *)(const void *)&ptr[(n) * 4])
#define MD5_GET(n) MD5_SET(n)
#else