]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
wifi: rtw89: mac: set MU group membership and position to registers
authorPing-Ke Shih <pkshih@realtek.com>
Tue, 27 Jan 2026 08:50:34 +0000 (16:50 +0800)
committerPing-Ke Shih <pkshih@realtek.com>
Fri, 30 Jan 2026 05:54:32 +0000 (13:54 +0800)
The WiFi 7 chips use different registers to configure MU group for
beamforming. Define specific registers and refactor the common flow.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Link: https://patch.msgid.link/20260127085036.44060-5-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/mac.c
drivers/net/wireless/realtek/rtw89/mac.h
drivers/net/wireless/realtek/rtw89/mac_be.c
drivers/net/wireless/realtek/rtw89/reg.h

index 4f0f17c499fa58215be07532a7619769c6d40396..8472f1a63951bf485c68061d724810a8907d22be 100644 (file)
@@ -4374,6 +4374,12 @@ static const struct rtw89_port_reg rtw89_port_base_ax = {
                    R_AX_PORT_HGQ_WINDOW_CFG + 3},
 };
 
+static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_ax = {
+       .position_en = {R_AX_GID_POSITION_EN0, R_AX_GID_POSITION_EN1},
+       .position = {R_AX_GID_POSITION0, R_AX_GID_POSITION1,
+                    R_AX_GID_POSITION2, R_AX_GID_POSITION3},
+};
+
 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev,
                                        struct rtw89_vif_link *rtwvif_link, u8 type)
 {
@@ -6770,6 +6776,8 @@ void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev,
 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
                                struct ieee80211_bss_conf *conf)
 {
+       const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
+       const struct rtw89_mac_mu_gid_addr *addr = mac->mu_gid;
        struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
        struct rtw89_vif_link *rtwvif_link;
        u8 mac_idx;
@@ -6789,20 +6797,20 @@ void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *
 
        p = (__le32 *)conf->mu_group.membership;
        rtw89_write32(rtwdev,
-                     rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx),
+                     rtw89_mac_reg_by_idx(rtwdev, addr->position_en[0], mac_idx),
                      le32_to_cpu(p[0]));
        rtw89_write32(rtwdev,
-                     rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx),
+                     rtw89_mac_reg_by_idx(rtwdev, addr->position_en[1], mac_idx),
                      le32_to_cpu(p[1]));
 
        p = (__le32 *)conf->mu_group.position;
-       rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx),
+       rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[0], mac_idx),
                      le32_to_cpu(p[0]));
-       rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx),
+       rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[1], mac_idx),
                      le32_to_cpu(p[1]));
-       rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx),
+       rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[2], mac_idx),
                      le32_to_cpu(p[2]));
-       rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx),
+       rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, addr->position[3], mac_idx),
                      le32_to_cpu(p[3]));
 }
 
@@ -7282,6 +7290,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
        .port_base = &rtw89_port_base_ax,
        .agg_len_ht = R_AX_AGG_LEN_HT_0,
        .ps_status = R_AX_PPWRBIT_SETTING,
+       .mu_gid = &rtw89_mac_mu_gid_addr_ax,
 
        .muedca_ctrl = {
                .addr = R_AX_MUEDCA_EN,
index 0c8614fc3000a79f9a7f0b380d079f36a9cfbae7..e71a71648ab8ca907c7070b7a74de2cada725dca 100644 (file)
@@ -1015,6 +1015,11 @@ struct rtw89_mac_size_set {
 
 extern const struct rtw89_mac_size_set rtw89_mac_size;
 
+struct rtw89_mac_mu_gid_addr {
+       u32 position_en[2];
+       u32 position[4];
+};
+
 struct rtw89_mac_gen_def {
        u32 band1_offset;
        u32 filter_model_addr;
@@ -1025,6 +1030,7 @@ struct rtw89_mac_gen_def {
        const struct rtw89_port_reg *port_base;
        u32 agg_len_ht;
        u32 ps_status;
+       const struct rtw89_mac_mu_gid_addr *mu_gid;
 
        struct rtw89_reg_def muedca_ctrl;
        struct rtw89_reg_def bfee_ctrl;
index 3a84cd5291485d23f0046717ed0d22ae680b1b54..dc66b1ee851ac5d24fff3ca9452cd9e88e27189e 100644 (file)
@@ -62,6 +62,12 @@ static const struct rtw89_port_reg rtw89_port_base_be = {
                    R_BE_PORT_HGQ_WINDOW_CFG + 3},
 };
 
+static const struct rtw89_mac_mu_gid_addr rtw89_mac_mu_gid_addr_be = {
+       .position_en = {R_BE_GID_POSITION_EN0, R_BE_GID_POSITION_EN1},
+       .position = {R_BE_GID_POSITION0, R_BE_GID_POSITION1,
+                    R_BE_GID_POSITION2, R_BE_GID_POSITION3},
+};
+
 static int rtw89_mac_check_mac_en_be(struct rtw89_dev *rtwdev, u8 mac_idx,
                                     enum rtw89_mac_hwmod_sel sel)
 {
@@ -3170,6 +3176,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
        .port_base = &rtw89_port_base_be,
        .agg_len_ht = R_BE_AGG_LEN_HT_0,
        .ps_status = R_BE_WMTX_POWER_BE_BIT_CTL,
+       .mu_gid = &rtw89_mac_mu_gid_addr_be,
 
        .muedca_ctrl = {
                .addr = R_BE_MUEDCA_EN,
index 9b2e97ed5c7d68d0821e0e3e4f4058c552a81fbe..9b605617c3f0b8c4b6786ddf0c98fb623361081e 100644 (file)
 #define BE_WMAC_RFMOD_160M 3
 #define BE_WMAC_RFMOD_320M 4
 
+#define R_BE_GID_POSITION0 0x10070
+#define R_BE_GID_POSITION0_C1 0x14070
+#define R_BE_GID_POSITION1 0x10074
+#define R_BE_GID_POSITION1_C1 0x14074
+#define R_BE_GID_POSITION2 0x10078
+#define R_BE_GID_POSITION2_C1 0x14078
+#define R_BE_GID_POSITION3 0x1007C
+#define R_BE_GID_POSITION3_C1 0x1407C
+#define R_BE_GID_POSITION_EN0 0x10080
+#define R_BE_GID_POSITION_EN0_C1 0x14080
+#define R_BE_GID_POSITION_EN1 0x10084
+#define R_BE_GID_POSITION_EN1_C1 0x14084
+
 #define R_BE_TX_SUB_BAND_VALUE 0x10088
 #define R_BE_TX_SUB_BAND_VALUE_C1 0x14088
 #define B_BE_PRI20_BITMAP_MASK GENMASK(31, 16)