]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
drm/amd/ras: Add unified interface to handle ras interrupts
authorYiPeng Chai <YiPeng.Chai@amd.com>
Mon, 8 Dec 2025 08:28:49 +0000 (16:28 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 17 Mar 2026 14:33:04 +0000 (10:33 -0400)
Add unified interface to handle ras interrupts, some redundant
interrupt function interfaces will be removed later.

Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h

index 4b86a58e81491dfae2ab523a8b6da4dffca00c33..d213eea71cffe9f94f67819c24aa204a10bd2f41 100644 (file)
@@ -535,6 +535,37 @@ int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev, void
        return ret;
 }
 
+int amdgpu_ras_mgr_dispatch_interrupt(struct amdgpu_device *adev, struct ras_ih_info *ih_info)
+{
+       struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);
+       uint64_t seq_no = 0;
+       int ret = 0;
+
+       if (!amdgpu_ras_mgr_is_ready(adev))
+               return -EPERM;
+
+       if (!ih_info)
+               return 0;
+
+       if (ih_info->block == RAS_BLOCK_ID__UMC) {
+               if (ras_mgr->ras_core->poison_supported) {
+                       seq_no = amdgpu_ras_mgr_gen_ras_event_seqno(adev, RAS_SEQNO_TYPE_DE);
+                       RAS_DEV_INFO(adev,
+                               "{%llu} RAS poison is created, no user action is needed.\n",
+                               seq_no);
+               }
+
+               ret = amdgpu_ras_process_handle_umc_interrupt(adev, ih_info);
+       } else if (ras_mgr->ras_core->poison_supported) {
+               ret = amdgpu_ras_process_handle_consumption_interrupt(adev, ih_info);
+       } else {
+               RAS_DEV_WARN(adev,
+                       "No RAS interrupt handler for non-UMC block with poison disabled.\n");
+       }
+
+       return ret;
+}
+
 int amdgpu_ras_mgr_handle_consumer_interrupt(struct amdgpu_device *adev, void *data)
 {
        if (!amdgpu_ras_mgr_is_ready(adev))
index 23c411c9823198609772692da897b680c2f8391b..4f44a917d48be6bfe5b12ecf23bb93c4cf07765f 100644 (file)
@@ -67,6 +67,7 @@ bool amdgpu_uniras_enabled(struct amdgpu_device *adev);
 int amdgpu_ras_mgr_handle_fatal_interrupt(struct amdgpu_device *adev, void *data);
 int amdgpu_ras_mgr_handle_controller_interrupt(struct amdgpu_device *adev, void *data);
 int amdgpu_ras_mgr_handle_consumer_interrupt(struct amdgpu_device *adev, void *data);
+int amdgpu_ras_mgr_dispatch_interrupt(struct amdgpu_device *adev, struct ras_ih_info *ih_info);
 int amdgpu_ras_mgr_update_ras_ecc(struct amdgpu_device *adev);
 int amdgpu_ras_mgr_reset_gpu(struct amdgpu_device *adev, uint32_t flags);
 uint64_t amdgpu_ras_mgr_gen_ras_event_seqno(struct amdgpu_device *adev,