{
const struct msm_mdss_data *data = msm_mdss->mdss_data;
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
- MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
+ MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
if (data->ubwc_bank_spread)
value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;
{
const struct msm_mdss_data *data = msm_mdss->mdss_data;
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) |
- MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
+ MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
if (data->macrotile_mode)
value |= MDSS_UBWC_STATIC_MACROTILE_MODE;
{
const struct msm_mdss_data *data = msm_mdss->mdss_data;
u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
- MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
+ MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
if (data->ubwc_bank_spread)
value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD;
if (hw_rev == MDSS_HW_MSM8996 ||
hw_rev == MDSS_HW_MSM8998)
- data->highest_bank_bit = 2;
+ data->highest_bank_bit = 15;
else
- data->highest_bank_bit = 1;
+ data->highest_bank_bit = 14;
return data;
}
static const struct msm_mdss_data msm8998_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_1_0,
- .highest_bank_bit = 2,
+ .highest_bank_bit = 15,
.reg_bus_bw = 76800,
};
static const struct msm_mdss_data qcm2290_data = {
/* no UBWC */
- .highest_bank_bit = 0x2,
+ .highest_bank_bit = 15,
.reg_bus_bw = 76800,
};
.ubwc_dec_version = UBWC_4_0,
.ubwc_swizzle = 4,
.ubwc_bank_spread = true,
- .highest_bank_bit = 0,
+ .highest_bank_bit = 13,
.macrotile_mode = true,
.reg_bus_bw = 74000,
};
.ubwc_dec_version = UBWC_4_3,
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
- .highest_bank_bit = 0,
+ .highest_bank_bit = 13,
.macrotile_mode = 1,
.reg_bus_bw = 74000,
};
.ubwc_dec_version = UBWC_2_0,
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
- .highest_bank_bit = 0x1,
+ .highest_bank_bit = 14,
.reg_bus_bw = 76800,
};
.ubwc_dec_version = UBWC_4_0,
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
- .highest_bank_bit = 1,
+ .highest_bank_bit = 14,
.macrotile_mode = true,
.reg_bus_bw = 74000,
};
static const struct msm_mdss_data sc8180x_data = {
.ubwc_enc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
- .highest_bank_bit = 3,
+ .highest_bank_bit = 16,
.macrotile_mode = true,
.reg_bus_bw = 76800,
};
.ubwc_dec_version = UBWC_4_0,
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
- .highest_bank_bit = 3,
+ .highest_bank_bit = 16,
.macrotile_mode = true,
.reg_bus_bw = 76800,
};
static const struct msm_mdss_data sdm670_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
- .highest_bank_bit = 1,
+ .highest_bank_bit = 14,
.reg_bus_bw = 76800,
};
static const struct msm_mdss_data sdm845_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
- .highest_bank_bit = 2,
+ .highest_bank_bit = 15,
.reg_bus_bw = 76800,
};
.ubwc_dec_version = UBWC_2_0,
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
- .highest_bank_bit = 1,
+ .highest_bank_bit = 14,
.reg_bus_bw = 76800,
};
static const struct msm_mdss_data sm7150_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
- .highest_bank_bit = 1,
+ .highest_bank_bit = 14,
.reg_bus_bw = 76800,
};
static const struct msm_mdss_data sm8150_data = {
.ubwc_enc_version = UBWC_3_0,
.ubwc_dec_version = UBWC_3_0,
- .highest_bank_bit = 2,
+ .highest_bank_bit = 15,
.reg_bus_bw = 76800,
};
.ubwc_dec_version = UBWC_2_0,
.ubwc_swizzle = 7,
.ubwc_bank_spread = true,
- .highest_bank_bit = 0x1,
+ .highest_bank_bit = 14,
.reg_bus_bw = 76800,
};
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_3_0,
.ubwc_swizzle = 1,
- .highest_bank_bit = 1,
+ .highest_bank_bit = 14,
};
static const struct msm_mdss_data sm6150_data = {
.ubwc_enc_version = UBWC_2_0,
.ubwc_dec_version = UBWC_2_0,
- .highest_bank_bit = 1,
+ .highest_bank_bit = 14,
.reg_bus_bw = 76800,
};
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
- .highest_bank_bit = 3,
+ .highest_bank_bit = 16,
.macrotile_mode = true,
.reg_bus_bw = 76800,
};
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
- .highest_bank_bit = 3,
+ .highest_bank_bit = 16,
.macrotile_mode = true,
.reg_bus_bw = 74000,
};
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
- .highest_bank_bit = 3,
+ .highest_bank_bit = 16,
.macrotile_mode = true,
.reg_bus_bw = 57000,
};
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
- .highest_bank_bit = 3,
+ .highest_bank_bit = 16,
.macrotile_mode = true,
.reg_bus_bw = 57000,
};
.ubwc_swizzle = 6,
.ubwc_bank_spread = true,
/* TODO: highest_bank_bit = 2 for LP_DDR4 */
- .highest_bank_bit = 3,
+ .highest_bank_bit = 16,
.macrotile_mode = true,
/* TODO: Add reg_bus_bw with real value */
};