Optimize maskstore when mask is 0 or -1 in UNSPEC_MASKMOV

gcc/ChangeLog:

	PR target/115843
	* config/i386/predicates.md (const0_or_m1_operand): New
	predicate.
	* config/i386/sse.md (*<avx512>_store<mode>_mask_1): New
	pre_reload define_insn_and_split.
	(V): Add V32BF,V16BF,V8BF.
	(V4SF_V8BF): Rename to ..
	(V24F_128): .. this.
	(*vec_concat<mode>): Adjust with V24F_128.
	(*vec_concat<mode>_0): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr115843.c: New test.

diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 5d0bb1e0f54adecd05a9f26cfa491645feaed68a..680594871de05c808578c6becbbfbc3136c1b00e 100644 (file)
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -825,6 +825,11 @@
   (and (match_code "const_int")
        (match_test "op == constm1_rtx")))
 
+;; Match 0 or -1.
+(define_predicate "const0_or_m1_operand"
+  (ior (match_operand 0 "const0_operand")
+       (match_operand 0 "constm1_operand")))
+
 ;; Match exactly eight.
 (define_predicate "const8_operand"
   (and (match_code "const_int")

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e44822f705b4b8fd7878d364a7acfd2937c05619..f54e966bdbb2261c19f4f7e34e3d89ceea1b751d 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -294,6 +294,7 @@
    (V16SI "TARGET_AVX512F && TARGET_EVEX512") (V8SI "TARGET_AVX") V4SI
    (V8DI "TARGET_AVX512F && TARGET_EVEX512")  (V4DI "TARGET_AVX") V2DI
    (V32HF "TARGET_AVX512F && TARGET_EVEX512") (V16HF "TARGET_AVX") V8HF
+   (V32BF "TARGET_AVX512F && TARGET_EVEX512") (V16BF "TARGET_AVX") V8BF
    (V16SF "TARGET_AVX512F && TARGET_EVEX512") (V8SF "TARGET_AVX") V4SF
    (V8DF "TARGET_AVX512F && TARGET_EVEX512")  (V4DF "TARGET_AVX") (V2DF "TARGET_SSE2")])
 
@@ -430,8 +431,8 @@
    (V16SF "TARGET_EVEX512")
    (V8DF "TARGET_EVEX512")])
 
-(define_mode_iterator V4SF_V8HF
-  [V4SF V8HF])
+(define_mode_iterator V24F_128
+  [V4SF V8HF V8BF])
 
 (define_mode_iterator VI48_AVX512VL
   [(V16SI "TARGET_EVEX512") (V8SI "TARGET_AVX512VL") (V4SI "TARGET_AVX512VL")
@@ -11543,8 +11544,8 @@
    (set_attr "mode" "V4SF,SF,DI,DI")])
 
 (define_insn "*vec_concat<mode>"
-  [(set (match_operand:V4SF_V8HF 0 "register_operand"       "=x,v,x,v")
-       (vec_concat:V4SF_V8HF
+  [(set (match_operand:V24F_128 0 "register_operand"       "=x,v,x,v")
+       (vec_concat:V24F_128
          (match_operand:<ssehalfvecmode> 1 "register_operand"     " 0,v,0,v")
          (match_operand:<ssehalfvecmode> 2 "nonimmediate_operand" " x,v,m,m")))]
   "TARGET_SSE"
@@ -11559,8 +11560,8 @@
    (set_attr "mode" "V4SF,V4SF,V2SF,V2SF")])
 
 (define_insn "*vec_concat<mode>_0"
-  [(set (match_operand:V4SF_V8HF 0 "register_operand"       "=v")
-       (vec_concat:V4SF_V8HF
+  [(set (match_operand:V24F_128 0 "register_operand"       "=v")
+       (vec_concat:V24F_128
          (match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "vm")
          (match_operand:<ssehalfvecmode> 2 "const0_operand")))]
   "TARGET_SSE2"
@@ -28574,6 +28575,26 @@
    (set_attr "memory" "store")
    (set_attr "mode" "<sseinsnmode>")])
 
+(define_insn_and_split "*<avx512>_store<mode>_mask_1"
+  [(set (match_operand:V 0 "memory_operand")
+       (unspec:V
+         [(match_operand:V 1 "register_operand")
+          (match_dup 0)
+          (match_operand:<avx512fmaskmode> 2 "const0_or_m1_operand")]
+         UNSPEC_MASKMOV))]
+  "TARGET_AVX512F && ix86_pre_reload_split ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  if (constm1_operand (operands[2], <MODE>mode))
+    emit_move_insn (operands[0], operands[1]);
+  else
+    emit_note (NOTE_INSN_DELETED);
+
+  DONE;
+})
+
 (define_expand "cbranch<mode>4"
   [(set (reg:CC FLAGS_REG)
        (compare:CC (match_operand:VI_AVX_AVX512F 1 "register_operand")

diff --git a/gcc/testsuite/gcc.target/i386/pr115843.c b/gcc/testsuite/gcc.target/i386/pr115843.c
new file mode 100644 (file)
index 0000000..00d8605
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr115843.c
@@ -0,0 +1,38 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx512vl --param vect-partial-vector-usage=2 -mtune=znver5 -mprefer-vector-width=512" } */
+/* { dg-final { scan-assembler-not "kxor\[bw]" } } */
+
+typedef unsigned long long BITBOARD;
+BITBOARD KingPressureMask1[64], KingSafetyMask1[64];
+
+void __attribute__((noinline))
+foo()
+{
+  int i;
+
+  for (i = 0; i < 64; i++) {
+    if ((i & 7) == 0) {
+      KingPressureMask1[i] = KingSafetyMask1[i + 1];
+    } else if ((i & 7) == 7) {
+      KingPressureMask1[i] = KingSafetyMask1[i - 1];
+    } else {
+      KingPressureMask1[i] = KingSafetyMask1[i];
+    }
+  }
+}
+
+BITBOARD verify[64] = {1, 1, 2, 3, 4, 5, 6, 6, 9, 9, 10, 11, 12, 13, 14, 14, 17, 17, 18, 19,
+  20, 21, 22, 22, 25, 25, 26, 27, 28, 29, 30, 30, 33, 33, 34, 35, 36, 37, 38,
+  38, 41, 41, 42, 43, 44, 45, 46, 46, 49, 49, 50, 51, 52, 53, 54, 54, 57, 57,
+  58, 59, 60, 61, 62, 62};
+
+int main()
+{
+  for (int i = 0; i < 64; ++i)
+    KingSafetyMask1[i] = i;
+  foo ();
+  for (int i = 0; i < 64; ++i)
+    if (KingPressureMask1[i] != verify[i])
+      __builtin_abort ();
+  return 0;
+}