KVM: arm64: vgic-v5: Remove use of __assign_bit() with a constant

Using __assign_bit() is very useful when the value of the bit is
not known at compile time. In all other cases, __set_bit() and
__clear_bit() are the correct tool for the job.

This also fixes an odd case of using VGIC_V5_NR_PRIVATE_IRQS as
the bit value...

Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Link: https://lore.kernel.org/r/20260520091949.542365-4-maz@kernel.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
index 7c146fccc968995b0b949711096d6cc01760da65..4d62b1c31fe8b623488965a18c3b494bf35ff657 100644 (file)
--- a/arch/arm64/kvm/vgic/vgic-v5.c
+++ b/arch/arm64/kvm/vgic/vgic-v5.c
@@ -25,13 +25,13 @@ static void vgic_v5_get_implemented_ppis(void)
         * If we have KVM, we have EL2, which means that we have support for the
         * EL1 and EL2 Physical & Virtual timers.
         */
-       __assign_bit(GICV5_ARCH_PPI_CNTHP, ppi_caps.impl_ppi_mask, 1);
-       __assign_bit(GICV5_ARCH_PPI_CNTV, ppi_caps.impl_ppi_mask, 1);
-       __assign_bit(GICV5_ARCH_PPI_CNTHV, ppi_caps.impl_ppi_mask, 1);
-       __assign_bit(GICV5_ARCH_PPI_CNTP, ppi_caps.impl_ppi_mask, 1);
+       __set_bit(GICV5_ARCH_PPI_CNTHP, ppi_caps.impl_ppi_mask);
+       __set_bit(GICV5_ARCH_PPI_CNTV, ppi_caps.impl_ppi_mask);
+       __set_bit(GICV5_ARCH_PPI_CNTHV, ppi_caps.impl_ppi_mask);
+       __set_bit(GICV5_ARCH_PPI_CNTP, ppi_caps.impl_ppi_mask);
 
        /* The SW_PPI should be available */
-       __assign_bit(GICV5_ARCH_PPI_SW_PPI, ppi_caps.impl_ppi_mask, 1);
+       __set_bit(GICV5_ARCH_PPI_SW_PPI, ppi_caps.impl_ppi_mask);
 
        /* The PMUIRQ is available if we have the PMU */
        __assign_bit(GICV5_ARCH_PPI_PMUIRQ, ppi_caps.impl_ppi_mask, system_supports_pmuv3());
@@ -146,9 +146,7 @@ int vgic_v5_init(struct kvm *kvm)
        /* We only allow userspace to drive the SW_PPI, if it is implemented. */
        bitmap_zero(kvm->arch.vgic.gicv5_vm.userspace_ppis,
                    VGIC_V5_NR_PRIVATE_IRQS);
-       __assign_bit(GICV5_ARCH_PPI_SW_PPI,
-                    kvm->arch.vgic.gicv5_vm.userspace_ppis,
-                    VGIC_V5_NR_PRIVATE_IRQS);
+       __set_bit(GICV5_ARCH_PPI_SW_PPI, kvm->arch.vgic.gicv5_vm.userspace_ppis);
        bitmap_and(kvm->arch.vgic.gicv5_vm.userspace_ppis,
                   kvm->arch.vgic.gicv5_vm.userspace_ppis,
                   ppi_caps.impl_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS);
@@ -197,7 +195,7 @@ int vgic_v5_finalize_ppi_state(struct kvm *kvm)
                /* Expose PPIs with an owner or the SW_PPI, only */
                scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) {
                        if (irq->owner || i == GICV5_ARCH_PPI_SW_PPI) {
-                               __assign_bit(i, kvm->arch.vgic.gicv5_vm.vgic_ppi_mask, 1);
+                               __set_bit(i, kvm->arch.vgic.gicv5_vm.vgic_ppi_mask);
                                __assign_bit(i, kvm->arch.vgic.gicv5_vm.vgic_ppi_hmr,
                                             irq->config == VGIC_CONFIG_LEVEL);
                        }