net: phy: qcom: Add PHY counter support

Add PHY counter functionality to the shared library. The implementation
is identical for the current QCA807X and QCA808X PHYs.

The PHY counter can be configured to perform CRC checking for both received
and transmitted packets. Additionally, the packet counter can be set to
automatically clear after it is read.

The PHY counter includes 32-bit packet counters for both RX (received) and
TX (transmitted) packets, as well as 16-bit counters for recording CRC
error packets for both RX and TX.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250715-qcom_phy_counter-v3-1-8b0e460a527b@quicinc.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/phy/qcom/qcom-phy-lib.c b/drivers/net/phy/qcom/qcom-phy-lib.c
index af7d0d8e81be5cd3ff8e38b65d0d52552d6945f7..965c2bb99a9b8702338b754e8a039e01cb205278 100644 (file)
--- a/drivers/net/phy/qcom/qcom-phy-lib.c
+++ b/drivers/net/phy/qcom/qcom-phy-lib.c
@@ -699,3 +699,78 @@ int qca808x_led_reg_blink_set(struct phy_device *phydev, u16 reg,
        return 0;
 }
 EXPORT_SYMBOL_GPL(qca808x_led_reg_blink_set);
+
+/* Enable CRC checking for both received and transmitted frames to ensure
+ * accurate counter recording. The hardware supports a 32-bit counter,
+ * configure the counter to clear after it is read to facilitate the
+ * implementation of a 64-bit software counter
+ */
+int qcom_phy_counter_config(struct phy_device *phydev)
+{
+       return phy_set_bits_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_CTRL,
+                               QCA808X_MMD7_CNT_CTRL_CRC_CHECK_EN |
+                               QCA808X_MMD7_CNT_CTRL_READ_CLEAR_EN);
+}
+EXPORT_SYMBOL_GPL(qcom_phy_counter_config);
+
+int qcom_phy_update_stats(struct phy_device *phydev,
+                         struct qcom_phy_hw_stats *hw_stats)
+{
+       int ret;
+       u32 cnt;
+
+       /* PHY 32-bit counter for RX packets. */
+       ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_15_0);
+       if (ret < 0)
+               return ret;
+
+       cnt = ret;
+
+       ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_PKT_31_16);
+       if (ret < 0)
+               return ret;
+
+       cnt |= ret << 16;
+       hw_stats->rx_pkts += cnt;
+
+       /* PHY 16-bit counter for RX CRC error packets. */
+       ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_RX_ERR_PKT);
+       if (ret < 0)
+               return ret;
+
+       hw_stats->rx_err_pkts += ret;
+
+       /* PHY 32-bit counter for TX packets. */
+       ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_TX_PKT_15_0);
+       if (ret < 0)
+               return ret;
+
+       cnt = ret;
+
+       ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_TX_PKT_31_16);
+       if (ret < 0)
+               return ret;
+
+       cnt |= ret << 16;
+       hw_stats->tx_pkts += cnt;
+
+       /* PHY 16-bit counter for TX CRC error packets. */
+       ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_CNT_TX_ERR_PKT);
+       if (ret < 0)
+               return ret;
+
+       hw_stats->tx_err_pkts += ret;
+
+       return 0;
+}
+EXPORT_SYMBOL_GPL(qcom_phy_update_stats);
+
+void qcom_phy_get_stats(struct ethtool_phy_stats *stats,
+                       struct qcom_phy_hw_stats hw_stats)
+{
+       stats->tx_packets = hw_stats.tx_pkts;
+       stats->tx_errors = hw_stats.tx_err_pkts;
+       stats->rx_packets = hw_stats.rx_pkts;
+       stats->rx_errors = hw_stats.rx_err_pkts;
+}
+EXPORT_SYMBOL_GPL(qcom_phy_get_stats);

diff --git a/drivers/net/phy/qcom/qcom.h b/drivers/net/phy/qcom/qcom.h
index 7f7151c8bacaa5d8cdc15e5629d0c329e4f20a25..5071e7149a11d86680de04cb7cf94df184086664 100644 (file)
--- a/drivers/net/phy/qcom/qcom.h
+++ b/drivers/net/phy/qcom/qcom.h
@@ -195,6 +195,17 @@
 #define AT803X_MIN_DOWNSHIFT                   2
 #define AT803X_MAX_DOWNSHIFT                   9
 
+#define QCA808X_MMD7_CNT_CTRL                  0x8029
+#define QCA808X_MMD7_CNT_CTRL_READ_CLEAR_EN    BIT(1)
+#define QCA808X_MMD7_CNT_CTRL_CRC_CHECK_EN     BIT(0)
+
+#define QCA808X_MMD7_CNT_RX_PKT_31_16          0x802a
+#define QCA808X_MMD7_CNT_RX_PKT_15_0           0x802b
+#define QCA808X_MMD7_CNT_RX_ERR_PKT            0x802c
+#define QCA808X_MMD7_CNT_TX_PKT_31_16          0x802d
+#define QCA808X_MMD7_CNT_TX_PKT_15_0           0x802e
+#define QCA808X_MMD7_CNT_TX_ERR_PKT            0x802f
+
 enum stat_access_type {
        PHY,
        MMD
@@ -212,6 +223,13 @@ struct at803x_ss_mask {
        u8 speed_shift;
 };
 
+struct qcom_phy_hw_stats {
+       u64 rx_pkts;
+       u64 rx_err_pkts;
+       u64 tx_pkts;
+       u64 tx_err_pkts;
+};
+
 int at803x_debug_reg_read(struct phy_device *phydev, u16 reg);
 int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
                          u16 clear, u16 set);
@@ -246,3 +264,8 @@ int qca808x_led_reg_brightness_set(struct phy_device *phydev,
 int qca808x_led_reg_blink_set(struct phy_device *phydev, u16 reg,
                              unsigned long *delay_on,
                              unsigned long *delay_off);
+int qcom_phy_counter_config(struct phy_device *phydev);
+int qcom_phy_update_stats(struct phy_device *phydev,
+                         struct qcom_phy_hw_stats *hw_stats);
+void qcom_phy_get_stats(struct ethtool_phy_stats *stats,
+                       struct qcom_phy_hw_stats hw_stats);