aarch64: Test TARGET_STREAMING instead of TARGET_STREAMING_SME

g:ede97598e2c recorded separate ISA requirements for streaming
and non-streaming mode.  The premise there was that AARCH64_FL_SME
should not be included in the streaming mode requirements, since:

(a) an __arm_streaming_compatible function wouldn't be in streaming
    mode if SME wasn't available.

(b) __arm_streaming_compatible functions only allow things that are
    possible in non-streaming mode, so the non-streaming architecture
    is enough to assemble the code, even if +sme isn't enabled.

(c) we reject __arm_streaming if +sme isn't enabled, so don't need
    to test it for individual intrinsics as well.

Later patches lean into this further.

This patch applies the same reasoning to the .md constructs for
base streaming-only SME instructions, guarding them with
TARGET_STREAMING rather than TARGET_STREAMING_SME.

gcc/
	* config/aarch64/aarch64.h (TARGET_SME): Expand comment.
	(TARGET_STREAMING_SME): Delete.
	* config/aarch64/aarch64-sme.md: Use TARGET_STREAMING instead of
	TARGET_STREAMING_SME.
	* config/aarch64/aarch64-sve2.md: Likewise.

diff --git a/gcc/config/aarch64/aarch64-sme.md b/gcc/config/aarch64/aarch64-sme.md
index 9215f51b01f8129b3cca336fe6274959c9acc8a8..8fca138314c2e8232ea1db6d0fdd90fb413cb2a4 100644 (file)
--- a/gcc/config/aarch64/aarch64-sme.md
+++ b/gcc/config/aarch64/aarch64-sme.md
@@ -481,7 +481,7 @@
           (match_operand:<VPRED> 2 "register_operand" "Upl")
           (match_operand:SME_ZA_I 3 "aarch64_sve_ldff1_operand" "Utf")]
          SME_LD1))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   "ld1<Vesize>\t{ za%0<hv>.<Vetype>[%w1, 0] }, %2/z, %3"
 )
 
@@ -496,7 +496,7 @@
           (match_operand:<VPRED> 3 "register_operand" "Upl")
           (match_operand:SME_ZA_I 4 "aarch64_sve_ldff1_operand" "Utf")]
          SME_LD1))]
-  "TARGET_STREAMING_SME
+  "TARGET_STREAMING
    && UINTVAL (operands[2]) < 128 / <elem_bits>"
   "ld1<Vesize>\t{ za%0<hv>.<Vetype>[%w1, %2] }, %3/z, %4"
 )
@@ -583,7 +583,7 @@
           (match_operand:SI 2 "register_operand" "Ucj")
           (match_operand:<VPRED> 3 "register_operand" "Upl")]
          SME_ST1))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   "st1<Vesize>\t{ za%1<hv>.<Vetype>[%w2, 0] }, %3, %0"
 )
 
@@ -598,7 +598,7 @@
                    (match_operand:SI 3 "const_int_operand"))
           (match_operand:<VPRED> 4 "register_operand" "Upl")]
          SME_ST1))]
-  "TARGET_STREAMING_SME
+  "TARGET_STREAMING
    && UINTVAL (operands[3]) < 128 / <elem_bits>"
   "st1<Vesize>\t{ za%1<hv>.<Vetype>[%w2, %3] }, %4, %0"
 )
@@ -663,7 +663,7 @@
           (match_operand:DI 3 "const_int_operand")
           (match_operand:SI 4 "register_operand" "Ucj")]
          SME_READ))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   "mova\t%0.<Vetype>, %2/m, za%3<hv>.<Vetype>[%w4, 0]"
 )
 
@@ -678,7 +678,7 @@
           (plus:SI (match_operand:SI 4 "register_operand" "Ucj")
                    (match_operand:SI 5 "const_int_operand"))]
          SME_READ))]
-  "TARGET_STREAMING_SME
+  "TARGET_STREAMING
    && UINTVAL (operands[5]) < 128 / <elem_bits>"
   "mova\t%0.<Vetype>, %2/m, za%3<hv>.<Vetype>[%w4, %5]"
 )
@@ -693,7 +693,7 @@
           (match_operand:DI 3 "const_int_operand")
           (match_operand:SI 4 "register_operand" "Ucj")]
          SME_READ))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   "mova\t%0.q, %2/m, za%3<hv>.q[%w4, 0]"
 )
 
@@ -707,7 +707,7 @@
           (match_operand:<VPRED> 2 "register_operand" "Upl")
           (match_operand:SVE_FULL 3 "register_operand" "w")]
          SME_WRITE))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   "mova\tza%0<hv>.<Vetype>[%w1, 0], %2/m, %3.<Vetype>"
 )
 
@@ -722,7 +722,7 @@
           (match_operand:<VPRED> 3 "register_operand" "Upl")
           (match_operand:SVE_FULL 4 "register_operand" "w")]
          SME_WRITE))]
-  "TARGET_STREAMING_SME
+  "TARGET_STREAMING
    && UINTVAL (operands[2]) < 128 / <elem_bits>"
   "mova\tza%0<hv>.<Vetype>[%w1, %2], %3/m, %4.<Vetype>"
 )
@@ -737,7 +737,7 @@
           (match_operand:VNx2BI 2 "register_operand" "Upl")
           (match_operand:SVE_FULL 3 "register_operand" "w")]
          SME_WRITE))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   "mova\tza%0<hv>.q[%w1, 0], %2/m, %3.q"
 )
 
@@ -917,7 +917,7 @@
           (match_operand:<VPRED> 2 "register_operand" "Upl")
           (match_operand:SME_ZA_SDI 3 "register_operand" "w")]
          SME_BINARY_SDI))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   "<optab>\tza%0.<Vetype>, %1/m, %2/m, %3.<Vetype>"
 )
 
@@ -1479,7 +1479,7 @@
           (match_operand:VNx16QI_ONLY 3 "register_operand" "w")
           (match_operand:VNx16QI_ONLY 4 "register_operand" "w")]
          SME_INT_MOP))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   "<optab>\tza%0.s, %1/m, %2/m, %3.b, %4.b"
 )
 
@@ -1494,7 +1494,7 @@
           (match_operand:VNx8HI_ONLY 3 "register_operand" "w")
           (match_operand:VNx8HI_ONLY 4 "register_operand" "w")]
          SME_INT_MOP))]
-  "TARGET_STREAMING_SME && TARGET_SME_I16I64"
+  "TARGET_STREAMING && TARGET_SME_I16I64"
   "<optab>\tza%0.d, %1/m, %2/m, %3.h, %4.h"
 )
 
@@ -1887,7 +1887,7 @@
           (match_operand:SME_MOP_HSDF 3 "register_operand" "w")
           (match_operand:SME_MOP_HSDF 4 "register_operand" "w")]
          SME_FP_MOP))]
-  "TARGET_STREAMING_SME
+  "TARGET_STREAMING
    && (<SME_ZA_SDF_I:elem_bits> == 32) == (<SME_MOP_HSDF:elem_bits> <= 32)"
   "<b><optab>\tza%0.<SME_ZA_SDF_I:Vetype>, %1/m, %2/m, %3.<SME_MOP_HSDF:Vetype>, %4.<SME_MOP_HSDF:Vetype>"
 )

diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md
index 38ecdd1ccc1f6aa0bcdee5b37269c526918d6cbf..a7b29daeba4021f6b1e0d1134b5755189fe87a6b 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve2.md
+++ b/gcc/config/aarch64/aarch64-sve2.md
@@ -560,7 +560,7 @@
            (match_operand:SVE_FULL_I 1 "register_operand")
            (match_operand:SVE_FULL_I 2 "register_operand"))
          (match_operand:SVE_FULL_I 3 "register_operand")))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   {@ [cons: =0,  1, 2, 3; attrs: movprfx]
      [       w, %0, w, w; *             ] <su>clamp\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>
      [     ?&w,  w, w, w; yes           ] movprfx\t%0, %1\;<su>clamp\t%0.<Vetype>, %2.<Vetype>, %3.<Vetype>
@@ -580,7 +580,7 @@
               UNSPEC_PRED_X)
             (match_operand:SVE_FULL_I 3 "register_operand"))]
          UNSPEC_PRED_X))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   {@ [cons: =0,  1, 2, 3; attrs: movprfx]
      [       w, %0, w, w; *             ] #
      [     ?&w,  w, w, w; yes           ] #
@@ -3182,7 +3182,7 @@
             [(match_operand:SVE_FULL 2 "register_operand")]
             UNSPEC_REVD_ONLY)]
          UNSPEC_PRED_X))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   {@ [ cons: =0 , 1   , 2 ; attrs: movprfx ]
      [ w        , Upl , 0 ; *              ] revd\t%0.q, %1/m, %2.q
      [ ?&w      , Upl , w ; yes            ] movprfx\t%0, %2\;revd\t%0.q, %1/m, %2.q
@@ -3198,7 +3198,7 @@
             UNSPEC_REVD_ONLY)
           (match_operand:SVE_FULL 3 "register_operand")]
          UNSPEC_SEL))]
-  "TARGET_STREAMING_SME"
+  "TARGET_STREAMING"
   {@ [ cons: =0 , 1   , 2 , 3  ; attrs: movprfx ]
      [ w        , Upl , w , 0  ; *              ] revd\t%0.q, %1/m, %2.q
      [ ?&w      , Upl , w , w  ; yes            ] movprfx\t%0, %3\;revd\t%0.q, %1/m, %2.q

diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 593319fd4723626bf95f475e79c1c7b12238b2dd..d17f40ce22e8f37e483b53fb0c9d33d7e88e6339 100644 (file)
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -339,12 +339,10 @@ constexpr auto AARCH64_FL_DEFAULT_ISA_MODE ATTRIBUTE_UNUSED
 #define TARGET_SVE2_SM4 (AARCH64_HAVE_ISA (SVE2_SM4) && TARGET_NON_STREAMING)
 
 /* SME instructions, enabled through +sme.  Note that this does not
-   imply anything about the state of PSTATE.SM.  */
+   imply anything about the state of PSTATE.SM; instructions that require
+   SME and streaming mode should use TARGET_STREAMING instead.  */
 #define TARGET_SME AARCH64_HAVE_ISA (SME)
 
-/* Same with streaming mode enabled.  */
-#define TARGET_STREAMING_SME (TARGET_STREAMING && TARGET_SME)
-
 /* The FEAT_SME_I16I64 extension to SME, enabled through +sme-i16i64.  */
 #define TARGET_SME_I16I64 AARCH64_HAVE_ISA (SME_I16I64)